Deep neural network (DNN)-based methodologies have shown impressive performance and robustness in the detection of abnormalities and decoding of multi-modal biosignals. While the use of DNNs provides promising classification and decoding capabilities, it also introduces significant design and cost challenges for the implementation of biomedical System on Chips (SoC). To address the increasing demand for advanced and efficient DNN-based healthcare solutions at the edge, we propose BioSeek, an agile design generation framework enhanced by cutting-edge large-language models (LLM). BioSeek offers a comprehensive solution to the design challenges associated with biosignal processors. The effectiveness of BioSeek is evaluated through the design generation of both application-specific and versatile biosignal processors, demonstrating performance that is competitive with existing solutions.

Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable the agile design of DCIM macros with optimal architectures, we present SynDCIM - a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. Testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.

In this paper, we present a wireless closed-loop neuromodulation platform dedicated to diabetes management through implants in various body locations, such as the brain, stomach, and pancreas. The system's key components comprise a System-on-Chip (SoC) featuring a maximum 64-channel neural recording block to explore both neural roots and muscles involved in diabetes emergence and interactions within diverse organs with superior spatial resolution, an energy-efficient Impulse Radio Ultra-Wideband (IR-UWB) wireless transmitter, and an 8-channel stimulator for highly selective organ targeting. These capabilities are further enhanced by an edge-based Artificial Intelligence (AI) mechanism for real-time analysis. Simulation results show a total power consumption of 31.16 μW per channel for the recording and wireless transmission units, while the stimulator, powered by an inductive link, offers adjustable output with a maximum current of 3 mA and a voltage compliance of 9 V. Additionally, AI implemented as a four-layer neural network (NN) model using a field-programmable gate array (FPGA) on a wearable system achieved an accuracy of 98.06% in test sets.

In the realm of implantable brain neural interfaces, a prominent challenge is the constraint of limited power, particularly in systems with a high channel count. Various generic and application-specific strategies have been proposed to enhance energy efficiency while preserving signal integrity, resulting in varying levels of effectiveness. We introduce in paper an innovative approach that employs an auxiliary bypass featuring a low-power, low-sampling-rate level-crossing analog-to-digital converter (LC-ADC) to exploit signal sparsity. This method facilitates adaptive power control of the core Successive Approximation Register analog-to-digital converter (SAR ADC), achieving a significant 65% reduction in power consumption compared to traditional high-precision SAR ADCs. The ADC is fabricated using a 40 nm technology node, providing a bandwidth range from 10 Hz to 1 MHz and attaining an effective number of bits (ENOB) reaching up to 10.56 bits, with a figure-of-merit (FoM) as low as 2.56 fJ/conversion. This advancement underscores the potential for enhanced energy efficiency in high-channel-count neural interfaces.

In this paper, we present a novel self-adaptive pseudo-resistor (A-PR) designed to enhance the performance of neurorecording front-end circuits in terms of settling time, linearity, and tunability. We validate the effectiveness of the proposed A-PR through the implementation of a capacitively- coupled instrumentation amplifier (CCIA) recording front-end using TSMC 40-nm process technology. The results demonstrate that the A-PR enables continuous recording with minimal interruptions, enhancing the system’s robustness and enabling more reliable acquisition of neural signals. Notably, the A-PR achieves a significant reduction in settling time, reaching the millisecond level—1000 times faster than conventional pseudo-resistors—while also exhibiting wide linear characteristics and easy tunability.

The increasing interests in building bio-signal recording and processing systems for personal healthcare applications have been hindered by the critical sampling energy consumption issues of conventional biomedical systems. To address these limits, we propose a comprehensive strategy centered around a low-power level-crossing analog-to-spike converter (LC-ASC). This strategy enables event-driven compressive sampling by leveraging signal sparsity, achieving lower average sampling rates than Nyquist sampling. Our strategy includes universal VerilogA LC-ASC models, evaluation tools, and a reconfigurable data interface for versatile digital processing. Specifically, we introduce an online open-source VerilogA LC-ASC model and compression performance calculation tools for evaluating its performance with different bio-signals. The implemented LC-ASC chip demonstrates very-low power consumption of 31.5125.3 nW validated through chip measurements. Additionally, the proposed reconfigurable data interface ensures seamless integration with synchronous and asynchronous digital processing modules without sacrificing system-level performance. These advancements pave the way for energy-efficient neuromorphic biomedical circuits and systems.

EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to be deployed at edge. Biologically inspired, a new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks is proposed in this work. This approach designs an activate and inhibit joint processing spiking neural network (AIPS-SNN) which reaches an accuracy of 85.6% on Nina Pro dataset. Furthermore, the AIPS-SNN is deployed on the proposed memristor based computation in-memory (CIM) system, the power efficiency and area efficiency of which reach 10.146 TOPS/W and 35.399 GOPS/mm2, respectively. The experimental results indicate that the proposed neuromorphic CIM engine is promising for edge deployment.