Optical Network-on-Chip (NoC), offering the advantages of low energy consumption, high bandwidth, and low latency, is a promising solution for on-chip communications of multi-core systems. However, on-chip lasers, a key element in optical NoCs, are a dominant source of power consumption. In this paper, we propose dynamic laser power scaling (DLPS), a fine-grained control strategy for minimizing laser power consumption while meeting the communication bandwidth required for the application. The proposed DLPS strategy intelligently switches among multiple operation modes based on the communication traffic pattern. Our experiments show that by introducing two new modes (standby, and intermediate data rate), DLPS can further reduce the communication energy for communication-intensive applications, compared to a simple on-off control strategy that dynamically turns lasers either completely on or off.

A network-on-chip (NoC), a redundancy-rich and thus relatively robust system-chip, is still vulnerable to defects due to its large-scale integration. Thus, it is desirable to analyze the NoC yield in an early design phase. A Monte Carlo (MC) approach was proposed for the NoC yield analysis at the system level; however, it is inefficient due to the requirement of a large number of simulation runs. In this paper, we propose a Gibbs sampling approach, which can efficiently generate failed NoC instances as simulation samples, for yield estimation. This approach significantly reduces the number of required simulation runs for obtaining an accurate yield estimation. Implementation issues, such as initial sample selection, calculation of conditional distributions, and stop criterion, to customize Gibbs sampling for the NoC yield analysis are discussed. Potential optimization opportunities to further improve Gibbs sampling's efficiency are also explored. Compared to the MC approach, our experimental results show that the proposed approach can reduce the simulation runtime by 5×-100× for a high-yield NoC (a failure rate at 10-2-10-5), while achieving the same level of accuracy for yield estimation.

Short-reach nanophotonic interconnects are promising to solve the communication bottleneck in data centers and chip-level scenarios. However, the nanophotonic interconnects are sensitive to process and thermal variations, especially for the microring structures, resulting in significant variation of an optical link's bit error rate (BER). In this paper, we propose a power-efficient adaptive tuning approach for nanophotonic interconnects to address the variation issues. During the adaptive tuning process, each nanophotonic interconnect is adaptively allocated just enough power to meet the BER requirement. The proposed adaptive tuning approach could reduce the photonic receiver power by 8% - 34% than the worst-case based fixed design while achieving the same BER. Our evaluation results show that the adaptive tuning approach scales well with the process variation, the thermal variation and the number of communication nodes, and can accommodate different types of NoC architectures and lasers.