Moving beyond the automation-driven paradigm of Industry 4.0, Industry 5.0 emphasizes human-centric industrial systems where human creativity and instincts complement precise and advanced machines. With this new paradigm, there is a growing need for resource-efficient and user-preferred manufac-turing solutions that integrate humans into industrial processes. Unfortunately, methodologies for incorporating human elements into industrial processes remain underdeveloped. In this work, we present the first pipeline for the creation of a human-centered Digital Twin (DT), leveraging Unreal Engine's MetaHuman technology to track worker alertness in real-time. Our findings demonstrate the potential of integrating Artificial Intelligence (AI) and human-centered design within Industry 5.0 to enhance both worker safety and industrial efficiency.

The complexity of current manufacturing systems is growing, increasing the complexity of testing and validating control software. Manufacturing software must be extensively tested to minimize errors that may lead to production stops or machine breakdowns. However, testing on real manufacturing systems is often impractical or limited to small portions of the real systems. This paper presents Frost, an open-source platform supporting early manufacturing software validation and testing. Frost is built on top of the Lingua Franca framework, which ensures deterministic execution, enhancing the reliability of software prototyping and testing. The proposed platform implements a set of reactors and classes designed to model the different parts of a manufacturing system, such as sensors, machines, control software, and communication infrastructure. The effectiveness and capabilities of the Frost platform are validated by comparing the overhead introduced and by implementing a digital twin of a real manufacturing system.

Split Computing (SC), where a Deep Neural Network (DNN) is intelligently split with a part of it deployed on an edge device and the rest on a remote server is emerging as a promising approach. It allows the power of DNNs to be leveraged for latency-sensitive applications that do not allow the entire DNN to be deployed remotely, while not having sufficient computation bandwidth available locally. In many such embedded systems scenarios, such as those in the automotive domain, computational resource constraints also necessitate Multi-Task Learning (MTL), where the same DNN is used for multiple inference tasks instead of having dedicated DNNs for each task, which would need more computing bandwidth. However, how to partition such a multi-tasking DNN to be deployed within a SC framework has not been sufficiently studied. This paper studies this problem, and MTL-Split, our novel proposed architecture, shows encouraging results on both synthetic and real-world data. The source code is available at https://github.com/intelligolabs/MTL-Split.

In the past decade, Deep Neural Networks (DNNs) achieved state-of-the-art performance in a broad range of problems, spanning from object classification and action recognition to smart building and healthcare. The flexibility that makes DNNs such a pervasive technology comes at a price: the computational requirements preclude their deployment on most of the resource-constrained edge devices available today to solve real-time and real-world tasks. This paper introduces a novel approach to address this challenge by combining the concept of predefined sparsity with Split Computing (SC) and Early Exit (EE). In particular, SC aims at splitting a DNN with a part of it deployed on an edge device and the rest on a remote server. Instead, EE allows the system to stop using the remote server and rely solely on the edge device’s computation if the answer is already good enough. Specifically, how to apply such a predefined sparsity to a SC and EE paradigm has never been studied. This paper studies this problem and shows how predefined sparsity significantly reduces the computational, storage, and energy burdens during the training and inference phases, regardless of the hardware platform. This makes it a valuable approach for enhancing the performance of SC and EE applications. Experimental results showcase reductions exceeding 4× in storage and computational complexity without compromising performance. The source code is available at https://github.com/intelligolabs/sparsity_sc_ee.

Creating a virtual model of a real system brings several advantages before its effective fabrication, especially in the design phases. Simulating a system is helpful for determining whether and what improvements need to be brought to the prototype or for testing changes given by the presence of faults. In this context exploiting the features of a gaming engine created mainly for video game purposes for simulating physical prototypes could reveal new research perspectives. Advanced rendering capabilities, physical simulation, and accuracy in describing different materials obtainable make this environment very attractive even beyond the gaming world. Another key feature that can be obtained with these simulators is the combination of accurately modeled physical properties and graphical rendering of physical behaviors. Together, they generate a visualization that is physically accurate and graphically realistic. For this reason, this article examines the development of behavioral models inside the Unreal Engine gaming environment, mainly based on the C++ language. The models created will be used for design analysis, performance monitoring, and improvement research. The model chosen as a case study is a digital twin of a DC Motor simulated in normal operating conditions and in the presence of faults.

Under the pressure of the Industry 4.0 revolution, and now with the European Chips Act, smart systems are becoming omnipresent in all industrial sectors, e.g., automotive and aerospace. Such systems contain digital and analog components belonging to several physical domains, e.g., electrical and mechanical. To ensure robustness, the whole system must be validated as early as possible in the development cycle, by taking into account all such domains, as recommended by the ISO 26262 standard in the case, e.g., of automotive systems. Unfortunately, validation techniques, including fault injection and simulation are not as advanced on the analog side as the digital counterpart: i) they are not fully standardized ii) they are highly domain-dependent, and iii) they are performed separately from the digital flow. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios, it is possible to improve the robustness of the analog part and, at the same time, to improve the quality of the digital part that controls the system functionality. A multi-domain case study containing a microcontroller and a three-axis accelerometer is presented to demonstrate the validity of the proposed approach in many industrial contexts.

The safety of aircraft heavily depends on the in-tegrity of the Landing Gear System (LGS). However, gathering real-world fault data to support effective Prognostic and Health Management (PHM) practices presents significant challenges. This work proposes a novel methodology for generating synthetic fault data using a multi-physics Simscape model of a landing gear deployment/retraction mechanism. The model incorporates specialized fault blocks designed to replicate various hydraulic failure modes, aiming to broaden the pool of fault data covering the most common failures. This approach promises to enhance maintenance strategies and facilitate the development of hybrid Model-Based and Data-Driven solutions. Ultimately, the results of this study will be used to understand the physics within the landing gear better and gather the necessary data to create an effective Digital Twin for predictive maintenance.

Smart systems contain digital and analog components of several physical domains, e.g., electrical and mechanical During the design phase, the fault injection, which checks the system functionality following the guidelines of ISO standard 26262, enhances the system’s robustness. Unfortunately, fault injection and simulation on the analog side are i) not fully standardized compared to their digital counterparts, ii) highly domain-dependent, and iii) performed separately from the digital. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios it is possible to improve the robustness of the analog part and simultaneously improve the quality of the digital part that controls the system functionality.

Over the last decade, the industrial world has been involved in a massive revolution guided by the adoption of digital technologies. In this context, complex systems like cyber-physical systems play a fundamental role since they were designed and realized by composing heterogeneous components. The combined simulation of the behavioral models of these components allows to reproduce the nominal behavior of the real system. Similarly, a smart system is a device that integrates heterogeneous components but in a miniaturized form factor. The development of smart or cyber-physical systems, in combination with faulty behaviors modeled for the different physical domains composing the system, enables to support advanced functional safety assessment at the system level. A methodology to create and inject multi-domain fault models in the analog side of these systems has been proposed by exploiting the physical analogy between the electrical and mechanical domains to infer a new mechanical fault taxonomy. Thus, standard electrical fault models are injected into the electrical part, while the derived mechanical fault models are injected directly into the mechanical part. The entire flow has been applied to two case studies: a direct current motor connected with a gear train, and a three-axis accelerometer.

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.

In-vehicle network architectures are evolving from a typical signal-based client-server paradigm to a service-oriented one, introducing flexibility for software updates and upgrades. While signal-based networks are static by nature, service-oriented ones can more easily evolve during and after the design phase. As a result, service-oriented protocols are becoming more prominent in automotive in-vehicle networks. While applications like infotainment are less sensitive to delays, others like sensing and control have more stringent timing and reliability requirements. Hence, wider adoption of service-oriented protocols requires addressing the timing analysis and predictability of such protocols, which is more challenging than in their signal-oriented counterparts. In service-oriented architectures, the discovery phase defines how clients find their required services. The time required to complete the discovery phase is an important parameter since it determines the readiness of a sub-system or even the vehicle. In this paper, we develop a formal timing analysis of the discovery phase of SOME/IP, which is an emerging service-oriented protocol being considered for adoption by several automotive Original Equipment Manufacturers (OEMs) and suppliers.

Industry 4.0 involves the integration of digital technologies, such as IoT, Big Data, and AI, into manufacturing and industrial processes to increase efficiency and productivity. As these technologies become more interconnected and interdependent, Industry 4.0 systems become more complex, which brings the difficulty of identifying and stopping anomalies that may cause disturbances in the manufacturing process. This paper aims to propose a diffusion-based model for real-time anomaly prediction in Industry 4.0 processes. Using a neuro-symbolic approach, we integrate industrial ontologies in the model, thereby adding formal knowledge on smart manufacturing. Finally, we propose a simple yet effective way of distilling diffusion models through Random Fourier Features for deployment on an embedded system for direct integration into the manufacturing process. To the best of our knowledge, this approach has never been explored before.

With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ongoing work to standardize the definition of defect models and coverage calculation methods in the IEEE P2427 draft standard, there is a lack of a unified and portable method to define defect templates that can be used to inject in a systematic way defects in an analog circuit. Each of the existing EDA tool sets for fault injection proposes its own proprietary method to specify how defects should be defined and injected. The proposed paper describes a Verilog-A-based approach to coding defect templates, which through compliance with the Verilog-A standard, warrants portability across compatible simulators. The approach has been validated on the circuits from the Analogue Benchmark Circuits made available by the IEEE P2427 working group.

Constructing a holistic digital twin of a system composed of multiple physical domains is crucial for various tasks. In particular, when the simulation is extended with faults, it becomes a very important resource to achieve robust functional safety analysis. This article proposes a new methodology to build non-electrical fault models for the thermal domain. Such thermal faults are defined through an electrical circuit representing the thermal behavior of the system, known as the Cauer network, based on the physical analogies between the two domains. Including this thermal representation in a multi-domain system allows to simulate the interconnections between different physical domains, thus achieving a more realistic system behavior and evaluating the mutual impact of different domains (e.g., mechanical, electrical and thermal). The entire methodology is applied to a complex case of study implemented by using Verilog-AMS as a proof of concept.

The heterogeneous nature of SystemC-AMS makes it a perfect candidate solution to support Cyber-Physical Production Systems (CPPSs), i.e., systems that are characterized by a tight interaction of the cyber part with the surrounding physical world and with manufacturing production processes. Nonetheless, the support for the modeling of physical and mechanical dynamics typical of production machinery goes far beyond the initial application scenario of SystemC-AMS, thus limiting its effectiveness and adoption in the production and manufacturing context. This paper starts with an analysis of the current adoption of SystemC-AMS to highlight the open points that still limit its effectiveness, with the goal of pinpointing current issues and to propose solutions that could improve its effectiveness, and make SystemC-AMS an essential resource also in the new Industry 4.0 scenario.

The core idea of flexible manufacturing is adapting to changes. In this domain, the machine is not confined to a single fixed type of process but can perform different jobs (e.g., cutting, drilling) in different ways (e.g., varying speed, tool, power consumption). This adaptability should be enabled by a detailed view of how the machines work. The idea is to perform machine scheduling by exploiting the dynamical models—expressed as differential equations—of manufacturing processes, i.e., both machines and production items. The main innovation in this paper is the ability to compute a machine’s schedule where the state of the product does not linearly evolve in time but is determined by the set of differential equations instead. Finding the schedule is defined as a multi-objective optimization problem—manufacturers may seek a trade-off between processing time, energy consumption, and other cost functions. The proposed optimization is evaluated using accurate process models, exemplifying how it works and harnesses the expressiveness of differential equations.

There are several languages for modeling a Cyber-Physical System (CPS). One of them is Verilog-AMS, which allows representing a system belonging to the electrical and mechanical physical domains in a single model through different disciplines. A framework for the automatic fault injection in the electrical and mechanical domains is proposed in this context. In particular, starting from a mechanical system, it is possible to represent it as an electrical circuit by exploiting the physical analogies. In the electrical domain, fault modeling and injection techniques are more advanced than in other physical domains. Extending the analogies to fault models makes it possible to apply the electrical fault models in the equivalent circuit to the mechanical system. These yields mechanical-level faulty behaviors, which can be injected into the mechanical domain, resulting in mechanical (physical) faults, depending on the component. It is finally shown an example of execution of this flow through a model of an electric motor, in which mechanical faults are injected. Simultaneously, the equivalent electrical faults are injected into the equivalent electrical circuit.

Digital twins of production lines do not focus solely on the management of the production process, they can also monitor and optimize other extra-functional aspects such as energy consumption and communications. This paper proposes the extension of digital twin concept in such directions. First, we extend the digital twin with models of energy consumption, that allow the monitoring of production line components throughout production lifetime. Then, we propose a flow to design the communication network starting from information obtained from the digital twin concerning the production, usage and flowing of information through the plant. All these methodologies start from the production line specification, then they enrich it with data collected during operation, and finally information is used to perform design and optimization. Results have been shown on a real Industry 4.0 research facility.

In this article, a predictive fault grouping based on the collection of faulty AC matrices at fault-free operating points is presented as a means to approximate the final distribution of faults in equivalence classes using a minimal computational effort. The method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself only to AC simulations with faults activated. The technique provides an approximation, since it does not characterize faults at the corresponding faulty operating point but instead looks at how they would modify the fault-free operating point once injected.The approximate grouping achieves an excellent correlation to the final classification based on the comparison of faulty transient wave-forms. It is not meant as a substitute for the traditional fault injection simulations but as a support to decision making. It allows prioritizing faults to characterize the possible failure modes with a minimum number of fault injections, pushing out fault injections which are estimated to marginally increase the learning.

There are plentiful successors of SPICE language for describing transistor-level designs. For most of them, the semantic matches those of SPICE, and only the syntax is changed. Others instead provide more default models or analysis tools. Consequently, a commercial tool is usually required for simulating, analyzing, and especially manipulating these languages. This article proposes a framework that relies on the shared semantic for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. First, the input description is parsed by a language-specific front-end which turns it into an in-memory abstract syntax tree that follows the common semantic. Then, the in-memory description can be subject to different user-defined manipulations built on top of a series of API or visitor/listener classes. Finally, the description goes through the desired back-end, transforming the in-memory description into the target transistor-level language. As a use-case for the proposed framework, we chose the process of analog fault injection. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. Therefore, the framework is completely written in C++, and its APIs are also interfaced with python. The entire framework is open-source and available on GitHub.

Today's factory machines are ever more connected with SCADA, MES, ERP applications as well as external systems for data analysis. Different types of network architectures must be used for this purpose. For instance, control applications at the lowest level are susceptible to delays and errors while data analysis with machine learning procedures requires to move a large amount of data without real-time constraints. Standard data formats, like Automation Markup Language (AML), have been established to document factory environment, machine placement and network deployment, however, no automatic technique is currently available in the context of Industry 4.0 to choose the best mix of network architectures according to spacial constraints, cost, and performance. We propose to fill this gap by formulating an optimization problem. First of all, spatial and communication requirements are extracted from the AML description. Then, the optimal interconnection of wired or wireless channels is obtained according to application objectives. Finally, this result is back-annotated to AML to be used in the life cycle of the production system. The proposed methodology is described through a small, but complete, smart production plant.

Pervasive computing requires to build systems every day more complex and heterogeneous. Smart devices must be able to carry on sensing and actuation alongside with computation and communication. As such, many different technologies must be packed within the same object. Digital HW and SW coexist with analog components and Micro-Electro-Mechanical systems capable of sensing and controlling the physical environment. For this reason, the design of such devices must rely on the integration of many different descriptions belonging to different design domains. The high-level of heterogeneity involved in the modeling phase of the system development makes harder the validation of the system functionality, since holistic system simulation would require the integration of many different simulators. In this article, we propose a set of automatic abstraction techniques for multi-disciplines analog components. Then, we define a scheduling strategy to integrate the execution of continuous-time analog sub-components with automatically abstracted models of the digital HW parts of the system. As a final result, the proposed methodology produces a C++ virtual platform providing a holistic simulation of complex and heterogeneous devices.

This paper proposes two approaches for the integration of cyber-physical systems in a production line in order to obtain predictions concerning the actual production, core operation in the context of Industry 4.0. The first approach relies on the Multi-Level paradigm where multiple descriptions of the same CPS are modeled with different levels of details. Then, the models are switched at runtime. The second approach relies on abstraction techniques of CPS maintaining a certain levels of details. The two approaches are validated and compared with a real use case scenario to identify the most effective simulation strategy.

Functional safety is a major concern in today's networked cyber-physical systems such as connected machines, autonomous vehicles, and intelligent environments. Simulation is a well-known methodology for the assessment of functional safety. Simulation models of networked cyber-physical systems are very heterogeneous relying on digital hardware, analog hardware, and network domains. Current functional safety assessment is mainly focused on digital hardware failures while minor attention is devoted to analog hardware and not at all to the interconnecting network. We propose a holistic methodology for simulation-based safety assessment in which safety mechanisms are tested in a simulation environment reproducing the high-level behavior of digital hardware, analog hardware, and network. Also faults are tested at high abstraction level to speed up analysis.

The amazing proliferation of communication technologies for embedded systems opens the way for completely new applications but forces designers to adopt new methodologies to meet time-to-market constraints. Computer-Aided Design (CAD) has been traditionally applied to computers and embedded systems in isolation without considering them as a global inter-connected system. The paper contributes to fill this gap by proposing 1) a communication-aware design flow for network-interconnected embedded systems and 2) a formal framework to efficiently synthesize their network aspects by formulating and solving an optimization problem. Presented case studies show the potentiality of the proposed approach to address heterogeneous scenarios, e.g., related to smart spaces up to the ever-more-mentioned Internet-of-Things.

Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this scenario, this paper proposes the automatic conversion of analog models to C++-based languages, to remove the overhead of co-simulation with traditional virtual platform tools. The proposed methodology allows to convert a given analog description to either: 1) a fully equivalent description or 2) an abstract representation for faster simulation which models only the aspects of interest. Effectiveness and correctness have been proved on a number of case studies that highlight the effectiveness and potentiality of the proposed methodology.

Modern smart systems are usually built by implementing SW functionalities executed on HW platforms composed of both digital and analog components. Validation is mainly implemented through simulation of the functional behavior of the entire smart system modeled by a Virtual Platform. It is thus crucial to achieve fast mixed-signal simulation by removing unnecessary overhead due to synchronization between multiple tools and unimportant details. This work proposes a methodology to abstract mixed-signal systems, by integrating digital and analog components in a homogeneous virtual platform model for efficient simulation. Two main contributions are provided: 1) an automatic abstraction technique for analog components, allowing to preserve only the details meaningful for the functional behavior of the entire platform by moving complexity from simulation to generation time and 2) a novel scheduling technique that exploits temporal decoupling and synchronization of digital and analog processes, to simulate them together in a homogeneous model.

Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current problem is the computational time required for implementing an analog fault simulation campaign. To this end, the work presented in this paper is an automatic procedure which: 1) injects faults in an analog circuit, 2) abstracts both faulty and fault-free models from the circuit to the functional level, 3) builds an efficient fault simulation framework. The processes of fault injection, faulty model abstraction and framework generation are reported in details, as well as how simulation is carried out. This abstraction process, which preserves the faulty behaviors, allows to reach a speed-up of some orders of magnitude and thus, making feasible an extensive analog faults campaign.

Multi-discipline components introduce problems when inserted within virtual platforms of Smart Systems for functional validation. This paper lists the most common emerging problems and it proposes a set of solutions to them. It presents a set of techniques, unified in an automatic abstraction methodology, useful to achieve fast analog mixed-signal simulation even when different physical disciplines and modeling styles are combined into a single analog model. The paper makes use of a complex case study. It deals with multiple-discipline descriptions, non-electrical conservative models, non-linear equation systems, and mixed time/frequency domain models. The original component behavior has been modeled in Verilog-AMS by using electrical, mechanical and kinematic equations. Then, it has been abstracted and integrated within a virtual platform of a mixed-signal smart system for efficient functional simulation.

In the last years an inversion of trend has brought new interest to the analog domain. Its integration within modern digital designs has led to the birth of the so called Analog and Mixed-Signal (AMS) systems. Functional safety assessment of such systems must be evaluated by instrumenting both the analog and digital parts. Such an activity can be simplified if these parts can be considered as an unique layer. Based on such an idea, this work brings them to a common ground by unifying the description language. Such a process is performed through settled procedures that abstract the AMS description to a common abstraction level (behavioral) and to a homogeneous high-level language (C++). This provides a speedup of two orders of magnitude in the fault simulation of an AMS platform.

Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.

The paper focuses on techniques for the verification of software implementing communication functionality in networked embedded systems. We discuss the merits and limitations of tools for the simulation of a networked embedded system executing the binary code of the network protocol stack. In particular, we compare different solutions to extend a virtual platform to simulate the node of interest in a realistic communication scenario involving different network nodes. We then explain how this solution has the potentiality to perform verification of the protocol stack, which would be a great asset for industry and academia to validate the communication software under development or use.