Peter Pleshko

dblp:171/1110 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Memory systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011966
An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966
Integrated circuit design
memory circuit design
0.011966
An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966
Memory systems
semiconductor memory
0.011966
An Investigation of the Potential of MOS Transistor Memories · IEEE Trans. Electron. Comput. 1966

Methods — techniques the papers use, named apart from their topics

performance characterization · 0.0
YearPublicationVenuePosition
1983 Advances in new display technology (Panel Session)
abstract
No abstract available.
Sol Sherr, Ifay Chang, Thomas Maloney, Peter Pleshko, Elliot Schlam, Peter Seats
SIGGRAPH4
1966 An Investigation of the Potential of MOS Transistor Memories
abstract
The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time.
Peter Pleshko, Lewis M. Terman
IEEE Trans. Electron. Comput.1