This paper presents an ultra-fine frequency offset synthesis (UFFOS) technique that achieves sub-parts-perbillion (sub-ppb, $\lt10^{-9}$) frequency resolution in FieldProgrammable Gate Array (FPGA)-based clock generation. To overcome the inherent limitation of conventional FPGA clocking techniques (e.g., PLLs/DLLs), where minimum frequency adjustments are restricted to the order of 1% ($10^{-3}$), UFFOS employs a novel architecture of cascaded phase interpolators (PIs) synchronized to a high-stability reference clock. This technique enables programmable sub-ppb frequency offsets through precise phase accumulation control. Implemented on an AMD Xilinx Virtex Ultrascale+ FPGA platform, UFFOS demonstrates frequency offsets ranging from $\mathbf{0. 9 ~ p p b}$ to 3.35 parts-per-million ($\mathbf{p p m}, \mathbf{1 0}^{\boldsymbol{-} \mathbf{6}}$). A comprehensive jitter decomposition analysis characterizes the synthesized clock’s time-domain performance. Furthermore, we propose a digital heterodyne frequency offset measurement (DHFOM) method capable of verifying sub-ppb-level frequency offsets with quantization errors on the order of parts-per-quadrillion (ppq, $10^{-15}$). Experimental validation confirms UFFOS as a robust solution for sub-ppb frequency offset generation, enabling applications demanding extreme frequency precision, including coherent optical communications, atomic clock synchronization, quantum computing control systems, distributed sensor networks, and next-generation softwaredefined radio architectures.

In modern high-speed communications systems, jitter tolerance testing becomes increasingly critical as signal rates continue to rise, playing a vital role in ensuring reliable data transmission and optimal system performance. As a core component of jitter tolerance testing, jitter injection must meet stringent precision and flexibility demands. This paper introduces a novel jitter injection module that integrates a programmable SiGe delay line (PDL) with an FPGA-based arbitrary signal generator, enabling flexible generation of diverse jitter profiles. The proposed solution enables cost-effective generation of Gaussian-distributed random jitter (RJ), sinusoidal/periodic jitter, and deterministic jitter (DJ) in unlimited combinations. Experimental results demonstrate injection of both periodic and random jitter components onto 28 GHz clock signals, with the module achieving ±7.4 femtosecond (fs) accuracy for random jitter and high flexibility in generating arbitrary profiles (e.g., sinusoidal jitter).

This paper presents an experimental comparison of multiplexing techniques for generating high-speed Non-Return-to-Zero (NRZ) test signals ranging from 28 to 64 Gbps using field-programmable gate arrays (FPGAs) and advanced SiGe components. Traditional high-speed signal synthesis methods, such as exclusive-OR (XOR) gates and multiplexers (MUXs), are evaluated for their performance in overcoming signal integrity challenges like jitter, edge-rate, and data-eye degradation. The study demonstrates that re-clocking input signals with high-speed flip-flops prior to XOR-based frequency doubling significantly reduces jitter, while DDR re-clocked 2:1 and 4:1 MUXs leverage dual-edge clocking to achieve higher data rates. Experimental results show that these techniques enhance signal quality, with metrics including total jitter (TJ) reduced to 7.88 ps and eye opening expanded to 77.84% at 28.125 Gbps. At 56.25 Gbps, the XOR gate alone yields a nearly closed eye opening of 1.39%, the combination of flip-flop and XOR gate improves it to 48.19%. The 2:1 MUX achieves the widest eye opening (53.31%). By exploiting the maximum operating rate of the 4:1 MUX, a 64 Gbps signal is achieved. This work highlights cost-effective, FPGA-based solutions for high-speed testing, addressing the critical need for affordable, scalable automated test equipment (ATE) required for next-generation integrated circuit validation.

March algorithms are essential for detecting functional memory faults, characterized by their linear complexity and adaptability to emerging technologies. However, the increasing complexity of fault types presents significant challenges to existing fault detection models regarding analytical efficiency and adaptability. This article introduces the test primitive (TP), a unified notation that characterizes March test sequences through a novel methodology that decouples fault detection operations from sensitization states. The proposed TP achieves platform independence and seamless integration of fault models, supported by rigorous theoretical proofs. These proofs establish the fundamental properties of the TP in terms of completeness, uniqueness, and conciseness, providing a theoretical foundation that ensures the decoupling method reduces the computational complexity of March algorithm analysis to$O(1)$. This reduction is analogous to Karnaugh map simplification in digital logic while enabling millisecond-level automated analysis. Experimental results demonstrate that the proposed method significantly enhances both analyzable fault coverage (FC) and detection accuracy, thereby addressing critical limitations of existing fault detection models.

Platooning, which is enabled by vehicle-to-vehicle (V2V) communication, is one of the most potential frameworks in the intelligent transport system (ITS) to enhance driving safety and improve traffic capacity. In a platoon, vehicles interact with each other by broadcasting beacons via Dedicated Short Range Communication (DSRC). In this work, we explore the impact of beacon transmission rate allocation on the network utility which involves not only network performance but also traffic safety and efficiency for the vehicular ad hoc network (VANET) composing of a single platoon. An optimization problem aiming at searching for an optimal beacon transmission rate allocation for platoon management is developed based on a network utility maximization framework. Particularly, adopting a synchronized P-persistent repetition (SPR) medium access control (MAC) protocol, an optimal beacon transmission rate allocation to achieve the network utility maximization, is obtained for a platoon at a certain cruise velocity. In the simulation, the correctness of the proposed approach is validated, and its advantages over the benchmark are demonstrated by comparisons.