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Gregory Martin Bednar

dblp:173/1767 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1974
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Integrated circuit design · 23%
Software engineering, system software, and programming languages
1 paper
Programming languages and type systems · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Programming languages and type systems
domain-specific languages		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974
Programming languages and type systems
language design		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974
Electronic design automation › logic synthesis
asynchronous circuit synthesis		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974
Electronic design automation
logic synthesis		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974
Integrated circuit design
digital circuit design		 0.011974
An Asynchronous Circuit Design Language (ACDL) · IEEE Trans. Computers 1974

Methods — techniques the papers use, named apart from their topics

automated synthesis · 0.0
YearPublicationVenuePosition
1974 An Asynchronous Circuit Design Language (ACDL)
abstract
This correspondence describes a special purpose Asynchronous Circuit Design Language (ACDL) for specifying the terminal behavior of asynchronous sequential circuits. The language is a valuable tool for formalizing and documenting asynchronous designs, as well as providing a user interface to a completely automated synthesis system. The language includes many special features which permit quick and precise specification of terminal behavior and is best suited for problems that are currently being described informally by word statements.
Gregory Martin Bednar, James H. Tracey
 IEEE Trans. Computers1