Demo Data from VLDB 2026 / reviewers in the wild / expert
Xingzhi Zhang
dblp:173/5774
· DBLP profile ↗
5ranked-venue papers
0as first author
2since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 1 since 2021Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Processor architecture and microarchitecture · 13% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.9 | 1 | 2025 | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing · ASPLOS (3) 2025 |
Electronic design automation
hardware verification and test |
0.9 | 1 | 2025 | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing · ASPLOS (3) 2025 |
Electronic design automation › hardware verification and test › processor verification
processor fuzzing |
0.9 | 1 | 2025 | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing · ASPLOS (3) 2025 |
Processor architecture and microarchitecture › out-of-order execution
out-of-order processor |
0.3 | 1 | 2025 | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing · ASPLOS (3) 2025 |
Methods — techniques the papers use, named apart from their topics
fuzzing · 1.7dynamic swappable memory · 1.7differential information flow tracking · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor FuzzingabstractTransient execution vulnerabilities have emerged as a critical threat to modern processors. Hardware fuzzing testing techniques have recently shown promising results in discovering transient execution bugs in large-scale out-of-order processor designs. However, their poor microarchitectural controllability and observability prevent them from effectively and efficiently detecting transient execution vulnerabilities. Jinyan Xu, Yangye Zhou, Xingzhi Zhang, Yinshuai Li, Qinhan Tan, Yinqian Zhang, Yajin Zhou, Wenbo Shen |
ASPLOS (3) | 3 |
| 2024 | MSFF-UNet: Image segmentation in colorectal glands using an encoder-decoder U-shaped architecture with multi-scale feature fusion
Chengdao Liu, Ziyang Peng, Xingzhi Zhang |
Multim. Tools Appl. | 4 |
| 2016 | Integrating POMDP and SARSA( \lambda λ ) for Service Composition with Incomplete Information
Xingzhi Zhang, Qi Yu 0001 |
ICSOC | 2 |
| 2016 | A multi-agent reinforcement learning approach to dynamic service composition
Xingguo Hu, Xingzhi Zhang, Mingzhu Gu |
Inf. Sci. | 4 |
| 2016 | Effective service composition using multi-agent reinforcement learning
Xingzhi Zhang, Qi Yu 0001, Xingguo Hu |
Knowl. Based Syst. | 3 |