The heavy ion radiation performance of NCringFET with single and dual-k spacers using both the inner and outer drain arrangements are investigated using 3D TCAD simulations. DC performance parameters, including ON current (Ion), OFF current (Ioff), and Ion/Ioffratio, are obtained for all NCringFET structures. The behavior of NCringFET to heavy ion irradiation is analyzed, and the device’s susceptible area is identified via single-event transient analysis. It was discovered that the most susceptible area for an inner drain arrangement is the centre of the drain, whereas the most susceptible area for an outer drain arrangement is the spacer near the drain. The source region is the least susceptible area for both outer and inner drain arrangements. Also, the single-event transient performance of NCringFET-based Inverters using both outer and inner drain arrangements are examined. NCringFET with an inner drain arrangement exhibits improved performance in radiation-prone areas due to its reduced collected charge, making it a more suitable choice for applications requiring high reliability and radiation tolerance at both the device level and circuit level.

Summary Tunnel field effect transistors are used for ultra‐low power application since it is challenging to operate CMOS at very low supply voltage. As tunnel field effect transistor has a very low subthreshold slope due to band to band tunneling (BTBT) mechanism, it has the potential to operate at very low operating voltage. It is necessary that the devices utilized in implantable bio‐medical applications and Internet of Everything (IoE) need to consume very low power. This work presents an analysis of Dual Material Double Gate Tunnel Field effect transistor (DMDG‐TFET). An analytical two dimensional (2D) model has been developed to obtain the analytical expressions for drain current. The 2D Poisson's equation has been used to calculate surface potential in the silicon channel using the superposition approximation, as it considers the short channel effects in the calculation of the current when compared to parabolic approximation. To validate the model, analytical results have been confirmed by comparing with the Sentaurus TCAD simulation results. A reduced subthreshold slope of 31.2 mV/decade is obtained in this paper. It shows that DMDG TFET is a promising candidate for ultra‐low power applications. The subthreshold swing obtained using superposition approximation is more optimized than that of parabolic approximation technique.