Gwangmu Lee

dblp:173/9806 · DBLP profile ↗
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8ranked-venue papers
3as first author
5since 2021 · last 2025
0009-0006-6464-355XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 5 · 2 first-author · 5 since 2021Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1
YearPublicationVenuePosition
2025 REFLECTA: Reflection-based Scalable and Semantic Scripting Language Fuzzing
Chibin Zhang, Gwangmu Lee, Qiang Liu 0034, Mathias Payer
AsiaCCS2
2024 SyzRisk: A Change-Pattern-Based Continuous Kernel Regression Fuzzer
abstract
Syzbot continuously fuzzes the full Linux kernel to discover latent bugs. Yet, around 75% of recent kernel bugs are caused by recent patches, dubbed regression bugs. Regression fuzzing prioritizes inputs that target recently or frequently patched code. However, this heuristic breaks down in the kernel environment as there are too many patches (and therefore too many targets).
Gwangmu Lee, Duo Xu 0006, Solmaz Salimi, Byoungyoung Lee, Mathias Payer
AsiaCCS1
2022 FuzzOrigin: Detecting UXSS vulnerabilities in Browsers through Origin Fuzzing
Jaewon Hur, Suhwan Song, Gwangmu Lee, Byoungyoung Lee
USENIX Security Symposium5
2022 MundoFuzz: Hypervisor Fuzzing with Statistical Coverage Testing and Grammar Inference
Cheolwoo Myung, Gwangmu Lee, Byoungyoung Lee
USENIX Security Symposium2
2021 Constraint-guided Directed Greybox Fuzzing
Gwangmu Lee, Woochul Shim, Byoungyoung Lee
USENIX Security Symposium1
2018 Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations
abstract
Spiking Neural Networks (SNNs) play an important role in neuroscience as they help neuroscientists understand how the nervous system works. To model the nervous system, SNNs incorporate the concept of time into neurons and inter-neuron interactions called spikes; a neuron's internal state changes with respect to time and input spikes, and a neuron fires an output spike when its internal state satisfies certain conditions. As the neurons forming the nervous system behave differently, SNN simulation frameworks must be able to simulate the diverse behaviors of the neurons. To support any neuron models, some frameworks rely on general purpose processors at the cost of inefficiency in simulation speed and energy consumption. The other frameworks employ specialized accelerators to overcome the inefficiency; however, the accelerators support only a limited set of neuron models due to their model-driven designs, making accelerator-based frameworks unable to simulate target SNNs. In this paper, we present Flexon, a flexible digital neuron which exploits the biologically common features shared by diverse neuron models, to enable efficient SNN simulations. To design Flexon, we first collect SNNs from prior work in neuroscience research and analyze the neuron models the SNNs employ. From the analysis, we observe that the neuron models share a set of biologically common features, and that the features can be combined to simulate a significantly larger set of neuron behaviors than the existing model-driven designs. Furthermore, we find that the features share a small set of computational primitives which can be exploited to further reduce the chip area. The resulting digital neurons, Flexon and spatially folded Flexon, are flexible, highly efficient, and can be easily integrated with existing hardware. Our prototyping results using TSMC 45 nm standard cell library show that a 12-neuron Flexon array improves energy efficiency by 6,186x and 422x over CPU and GPU, respectively, in a small footprint of 9.26 mm2. The results also show that a 72-neuron spatially folded Flexon array incurs a smaller footprint of 7.62 mm2 and achieves geomean speedups of 122.45x and 9.83x over CPU and GPU, respectively.
Dayeol Lee, Gwangmu Lee, Dongup Kwon, Sunghwa Lee, Youngsok Kim, Jangwoo Kim
ISCA2
2018 DynaMix: Dynamic Mobile Device Integration for Efficient Cross-device Resource Sharing
Dongju Chae, Joonsung Kim 0001, Gwangmu Lee, Hanjun Kim 0001, Kyung-Ah Chang, Hyogun Lee, Jangwoo Kim
USENIX ATC3
2015 Architecture-aware automatic computation offload for native applications
abstract
Although mobile devices have been evolved enough to support complex mobile programs, performance of the mobile devices is lagging behind performance of servers. To bridge the performance gap, computation offloading allows a mobile device to remotely execute heavy tasks at servers. However, due to architectural differences between mobile devices and servers, most existing computation offloading systems rely on virtual machines, so they cannot offload native applications. Some offloading systems can offload native mobile applications, but their applicability is limited to well-analyzable simple applications. This work presents automatic cross-architecture computation offloading for general-purpose native applications with a prototype framework that is called Native Offloader. At compile-time, Native Offloader automatically finds heavy tasks without any annotation, and generates offloading-enabled native binaries with memory unification for a mobile device and a server. At run-time, Native Offloader efficiently supports seamless migration between the mobile device and the server with a unified virtual address space and communication optimization. Native Offloader automatically offloads 17 native C applications from SPEC CPU2000 and CPU2006 benchmark suites without a virtual machine, and achieves a geomean program speedup of 6.42× and battery saving of 82.0%.
Gwangmu Lee, Hyunjoon Park, Seonyeong Heo, Kyung-Ah Chang, Hyogun Lee, Hanjun Kim 0001
MICRO1