Demo Data from VLDB 2026 / reviewers in the wild / expert
Cheng-Yi Chou
dblp:174/8279
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Cloud and datacenter computing · 44% Memory systems · 44% Processor architecture and microarchitecture · 13% | |
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines › binary translation
dynamic binary translation |
0.2 | 1 | 2016 | Optimizing Control Transfer and Memory Virtualization in Full System Emulators · ACM Trans. Archit. Code Optim. 2016 |
Cloud and datacenter computing › virtualization
memory virtualization |
0.2 | 1 | 2016 | Optimizing Control Transfer and Memory Virtualization in Full System Emulators · ACM Trans. Archit. Code Optim. 2016 |
Memory systems › virtual memory management
software TLB |
0.2 | 1 | 2016 | Optimizing Control Transfer and Memory Virtualization in Full System Emulators · ACM Trans. Archit. Code Optim. 2016 |
Methods — techniques the papers use, named apart from their topics
indirect branch target caching · 0.5block chaining · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Optimizing Control Transfer and Memory Virtualization in Full System EmulatorsabstractFull system emulators provide virtual platforms for several important applications, such as kernel and system software development, co-verification with cycle accurate CPU simulators, or application development for hardware still in development. Full system emulators usually use dynamic binary translation to obtain reasonable performance. This paper focuses on optimizing the performance of full system emulators. First, we optimize performance by enabling classic control transfer optimizations of dynamic binary translation in full system emulation, such as indirect branch target caching and block chaining. Second, we improve the performance of memory virtualization of cross-ISA virtual machines by improving the efficiency of the software translation lookaside buffer (software TLB). We implement our optimizations on QEMU, an industrial-strength full system emulator, along with the Android emulator. Experimental results show that our optimizations achieve an average speedup of 1.98X for ARM-to-X86-64 QEMU running SPEC CINT2006 benchmarks with train inputs. Our optimizations also achieve an average speedup of 1.44X and 1.40X for IA32-to-X86-64 QEMU and AArch64-to-X86-64 QEMU on SPEC CINT2006. We use a set of real applications downloaded from Google Play as benchmarks for the Android emulator. Experimental results show that our optimizations achieve an average speedup of 1.43X for the Android emulator running these applications. Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu |
ACM Trans. Archit. Code Optim. | 3 |