With the advent of Machine Learning (ML), predictive EDA tools are becoming the next hot topic of research in the EDA community, and researchers are working on ML-based tools to predict the performance of the EDA tool. As the designs become complex, there is a need to start the design using higher levels of abstraction, such as High-Level Synthesis (HLS) tools in FPGA and SoC design flows. Quick prediction of performance-related parameters of the final design after the C-synthesis stage, can help in rapid design closure. Even though multiple papers exist in the domain of post routing performance prediction of HLS tools, there are no standard benchmarks available to compare the performance and accuracy of the predictive models. In this paper, we have presented MLSBench, a collection of around 5000 synthesizable designs written in C and C++. We provide a methodology to generate designs with various variations from a single design, which creates a potential for creating newer designs and enlarging the database in the future. This is followed by analysis, and validating the generated designs are indeed different. This allows designers to create generalized machine-learning-based models that are not overfitted to a small dataset. We also perform statistical analysis for measuring the design diversity by synthesizing them using Xilinx-Vivado HLS for Zynq 7000 device series.

The floorplanning problem in FPGA has been a topic of research for more than a decade. Although the floorplanning problem has been thoroughly explored for homogeneous FPGAs, very less work has been done for heterogeneous FPGAs. In this paper, we have designed a floorplanner for partially reconfigurable design in heterogeneous FPGAs which takes into consideration the diversity of resources present inside the FPGA device and their locations. The floorplanner is based on fixed outline simulated annealing algorithm. We proposed a priority based sorting algorithm mimicking Olympic Medal Tally for initial floorplanning which is a preprocessing step for simulated annealing. Also, a White Space detection algorithm is proposed for efficient management of white space inside the FPGA device. We defined a cost function, which consists of weighed sum of wirelength, area and resource wastage, and minimized this cost function using simulated annealing. In this work, we also described a method to calculate two different types of resource wastage and suggested a method to reduce it. The performance of our floorplanner is evaluated using MCNC benchmarks on Xilinx Virtex 5 FPGA architecture. We have compared our proposed floorplanner with other results reported in the literature and observed substantial improvement in the overall wirelength as well as the execution time. Finally, we integrated our floorplanner with Xilinx PlanAhead to automate the floorplanning process. We generate the floorplan of a partially reconfigurable median filter, which consists of seven reconfigurable regions. When a comparison is made between the manually generated floorplan and the automatic floorplan generated by our tool, a significant improvement is observed in terms of parameters like total area occupied by the reconfigurable regions, frequency of the operation and total time required by PlanAhead to place and route the design.