Versatile Place and Route (VPR) enabled the exploration of diverse FPGA architectures. OpenFPGA extended VPR through bitstream generation and added silicon compilation. Our work is one of several efforts to use this combination to build commercial devices, which, to achieve competitiveness, has necessitated several improvements to routing and elsewhere for area, power, and performance. Fitting to the MCNC and VTR benchmarks using this work, our first improved routing pattern yields a 22% reduction in metal loading, a 14% reduction in routing multiplexer input pin count per function tile, and a 10% reduction in source to farthest sink paths. For this, routed length increased 5%, the proportion of net detours increased 11%, router heap operations increased 16%, and router iterations increased 42%, as the unmodified VPR router worked harder on routing with fewer switches but without introducing any routing failures. This work provides the first steps to a routing compiler for OpenFPGA/VPR, much as ASIC/SoC flows use a memory compiler.

Following the footsteps of the open-source software movement that is at the foundation of many fundamental infrastructures today, e.g., Linux, the internet, etc., a growing amount of open-source hardware initiatives have been impacting our field, e.g., the RISC-V ISA, Open chiplet standards, etc.

This paper describes architectural enhancements in Intel® Agilex™ FPGAs and SoCs. Agilex devices are built on Intel's 10nm process and feature next-generation programmable fabric, tightly coupled with a quad-core ARM processor subsystem, a secure device manager, IO and memory interfaces, and multiple companion transceiver tile choices. The Agilex fabric features multiple logic block enhancements that significantly improve propagation delays and integrate more effectively with the second-generation HyperFlexAgilex™ pipelined routing architecture. Routing connections are re-designed to be point-to-point, dropping intermediate connections featured in prior FPGA generations and replacing them with a wider variety of shorter wire types. Fine-grain programmable clock skew and time-borrowing were introduced throughout the fabric to augment the slack-balancing capabilities of HyperFlex registers. DSP capabilities are also extended to natively support new INT9/BFLOAT16/FP16 formats. Together, along with process and circuit enhancements, these changes support more than 40% performance improvement over the Stratix® 10 family of FPGAs.

The Stratix 10 project started with aggressive performance, size, and feature goals, all to be met on a lean schedule. Meeting these performance goals led to a restructuring of the entire configurable clock system into a regular gridded network, which subdivided the device into a composable system of "sectors". Sectors aligned with the needs of the project schedule, since they allowed complexity -- of specification, design, and validation -- to be addressed through "divide and conquer". Similarly, the customary "out-of-band" FPGA management functions including initialization, configuration, test, redundancy, scrubbing, and so on, were reconstituted to run on a collection of per-sector and supervisory processors interconnected by a NoC, whose distributed software would replace centralized tightly coupled finite state machines. This softwarization and parallelization reduced risk, increased flexibility, and increased data bandwidth. During development, parallel teams separately exercised each sector type and its local processor software via the sector's clock and NoC ports, accelerating validation on design databases two orders of magnitude smaller compared to previous methodologies. Even complex features can be added by including new NoC packet types and software rather than painfully adding wires to a rigid floor-plan.

We present the clock architecture of the Stratix?10 FPGA, which uses a routable clock network rather than the fixed clock networks of previous generations. We describe the flexibility provided by this routable clock network and how arbitrarily sized clock trees can be synthesized and placed anywhere on the FPGA. We show how this capability to generate customized clock trees can provide better performance through reduced clock loss while maintaining the ability to handle the large number of clock domains that modern systems require. We experimentally demonstrate how a routable clock tree reduces the clock loss of the user design implementation by up to 6% of clock insertion delay.