FPGAs are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are still area, performance, and energy efficiency gaps between FPGAs and ASICs. In this work, we propose a new FPGA architecture to narrow the energy efficiency gap. Since more than 62% of FPGA power is consumed in its interconnect, we target power consumption of the interconnect and try to reduce dynamic power consumption of this part using low-swing signaling technique. To implement low-swing signaling, high-to-low and low-to-high voltage level converters are added to the switch boxes and connection blocks of the basic architecture. Simulation results on 20 largest MCNC circuits and 19 computational benchmarks confirm that the proposed architecture achieves an average of 13.5% total power reduction with the cost of less than 1% area and delay overhead. To the authors? knowledge, the proposed architecture in this work is the first architecture that provides low-swing signaling for single driver unidirectional routing scheme. Moreover, the proposed architecture has the maximum CAD tool flexibility and no extra constraint is required for the placement and routing algorithms.