Andrew M. Keller

dblp:175/6231 · DBLP profile ↗
← Back
4ranked-venue papers
2as first author
1since 2021 · last 2022
0000-0002-6285-5288ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 82% Reconfigurable computing and FPGAs · 10% Cloud and datacenter computing · 8%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
soft errors
0.412019
Impact of Soft Errors on Large-Scale FPGA Cloud Computing · FPGA 2019
Hardware reliability and fault tolerance › radiation effects
radiation-induced faults
0.212016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing · FPGA 2016
Hardware reliability and fault tolerance › soft errors
single-event upset
0.212016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing · FPGA 2016
Hardware reliability and fault tolerance › redundancy › modular redundancy
triple modular redundancy
0.212016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing · FPGA 2016
Hardware reliability and fault tolerance
fault injection
0.112019
Impact of Soft Errors on Large-Scale FPGA Cloud Computing · FPGA 2019
Cloud and datacenter computing › cloud infrastructure
FPGA-based cloud computing
0.112019
Impact of Soft Errors on Large-Scale FPGA Cloud Computing · FPGA 2019
Reconfigurable computing and FPGAs › FPGA-based processor implementation
soft-core processor
0.112016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing · FPGA 2016
Reconfigurable computing and FPGAs › FPGA architecture
SRAM-based FPGA
0.112016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing · FPGA 2016

Methods — techniques the papers use, named apart from their topics

fault injection · 0.6orbit failure rate estimation · 0.2heavy ion radiation testing · 0.2
YearPublicationVenuePosition
2022 The Impact of Terrestrial Radiation on FPGAs in Data Centers
abstract
Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.
Andrew M. Keller, Michael J. Wirthlin
ACM Trans. Reconfigurable Technol. Syst.1
2019 Impact of Soft Errors on Large-Scale FPGA Cloud Computing
abstract
FPGAs are being used in large numbers within cloud computing to provide high-performance, low-power alternatives to more traditional computing structures. While FPGAs provide a number of important benefits to cloud computing environments, they are susceptible to radiation-induced soft errors, which can lead to silent data corruption or system instability. Although soft errors within a single FPGA occur infrequently, soft errors in large-scale FPGAs systems can occur at a relatively high rate. This paper investigates the failure rate of several FPGA applications running within an FPGA cloud computing node by performing fault injection experiments to determine the susceptibility of these applications to soft-errors. The results from these experiments suggest that silent data corruption will occur every few hours within a 100,000 node FPGA system and that such a system can only maintain high-levels of reliability for short periods of operation. These results suggest that soft-error detection and mitigation techniques may be needed in large-scale FPGA systems.
Andrew M. Keller, Michael J. Wirthlin
FPGA1
2018 Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental Placement
abstract
TMR combined with configuration scrubbing is an effective technique to mitigate against radiation-induced CRAM upsets on SRAM-based FPGAs. However, its effectiveness is limited by low-level common mode failures due to the physical mapping of a design to the FPGA device. This paper describes how common mode failures are introduced during the implementation process and introduces an approach for resolving them through a custom incremental placement tool for Xilinx 7-Series FPGAs. Multiple designs across multiple generations of devices are shown to be sensitive to common mode failures. Applying the incremental placement technique yields an improvement of 10,721x over an unmitigated design through fault-injection testing. Radiation testing is then performed to show that the of this technique is 91,500 days in GEO orbit, a 367x improvement over the unmitigated design and a 5x improvement over baseline TMR.
Matthew Cannon, Andrew M. Keller, Michael J. Wirthlin
FCCM2
2016 SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing
abstract
Processors are an essential component in most satellite payload electronics and handle a variety of functions including command handling and data processing. There is growing interest in implementing soft processors on commercial FPGAs within satellites. Commercial FPGAs offer reconfigurability, large logic density, and I/O bandwidth; however, they are sensitive to ionizing radiation and systems developed for space must implement single-event upset mitigation to operate reliably. This paper investigates the improvements in reliability of a LEON3 soft processor operating on a SRAM-based FPGA when using triple-modular redundancy and other processor-specific mitigation techniques. The improvements in reliability provided by these techniques are validated with both fault injection and heavy ion radiation tests. The fault injection experiments indicate an improvement of 51× and the radiation testing results demonstrate an average improvement of 10×. Orbit failure rate estimations were computed and suggest that the TMR LEON3 processor has a mean-time to failure of over 76 years in a geosynchronous orbit.
Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey T. Draper
FPGA2