Demo Data from VLDB 2026 / reviewers in the wild / expert
Luke Andrew Miller
dblp:176/4915
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 77% Hardware accelerators and domain-specific architectures · 23% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › signal processing accelerator
radar signal processing accelerator |
0.1 | 1 | 2016 | The Role of FPGAs in the Push to Modern and Ubiquitous Arrays · Proc. IEEE 2016 |
Methods — techniques the papers use, named apart from their topics
FPGA architecture evaluation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | The Role of FPGAs in the Push to Modern and Ubiquitous ArraysabstractField-programmable gate arrays (FPGAs) are finding greater use in commercial and military arrays for radar, communications, and other applications, thanks to recent advances in FPGA processing throughput, reduced power consumption, and faster input/output (I/O) interfaces with reduced pin counts. This paper describes how the latest in commercially available FPGAs address new forms of digital array architectures. A radar array design example illustrates how to select an FPGA for a given performance requirement. Luke Andrew Miller |
Proc. IEEE | 1 |