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H. Robert Downs

dblp:177/1208 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1973
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 33% Storage systems · 33% Embedded and real-time systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
data management		 0.011973
Real-Time Algorithms and Data Management on Illiac IV · IEEE Trans. Computers 1973
Parallel and multicore computing › array processor
parallel array processor		 0.011973
Real-Time Algorithms and Data Management on Illiac IV · IEEE Trans. Computers 1973
Embedded and real-time systems › real-time computer vision
real-time tracking		 0.011973
Real-Time Algorithms and Data Management on Illiac IV · IEEE Trans. Computers 1973

Methods — techniques the papers use, named apart from their topics

parallel algorithm · 0.0data organization · 0.0
YearPublicationVenuePosition
1973 Real-Time Algorithms and Data Management on Illiac IV
abstract
In order to use the Illiac IV array processor efficiently it is necessary to have different types of data management techniques than those which are used in a serial computer. This paper describes the data organization and management techniques that were developed for a particular real-time application. The particular problems considered are: 1) the tracking of objects at different rates; 2) the rearrangement of data sets as rates are changed and objects are inserted or deleted; and 3) the ``association'' of new returns with existing tracks. The techniques described here are for a particular application but they illustrate the kind of techniques required for parallel array processors and they may be generalized to a number of other potential applications.
H. Robert Downs
 IEEE Trans. Computers1