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Dhirubhai V. Kanani

dblp:177/1236 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1973
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
computer arithmetic		 0.011973
A Note on Conditional-Sum Addition for Base - 2 Systems · IEEE Trans. Computers 1973
Processor architecture and microarchitecture › computer arithmetic
negative base arithmetic		 0.011973
A Note on Conditional-Sum Addition for Base - 2 Systems · IEEE Trans. Computers 1973
YearPublicationVenuePosition
1973 A Note on Conditional-Sum Addition for Base - 2 Systems
abstract
Conditional-sum addition in a -2 base system and its comparison with normal binary conditional-sum addition is discussed. It is found that approximately 2.0 to 2.5 times as much hardware is required for this high-speed addition method in the negative binary system as compared to the positive binary system.
Dhirubhai V. Kanani, Kenneth H. O'Keefe
 IEEE Trans. Computers1