This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.

Given a synchronous sequential machine M, this correspondence deals with the fault-tolerant realization M of M and also its fail-safe realization M on the assumption that the faults that can occur to the circuitry of M or M are of permanent stuck-at type and the total number of faults can be at most some preset positive integer r. First, the realization of M or M is derived for r = 1 and then the same idea is extended to have the realization for any arbitrary r. It has been shown that the realization of M is such that it is also able to tolerate faults of nonpermanent nature.

This correspondence suggests an improved characterization of Boolean functions based on parameters, for unate cascade (UC) realizability. Using this characterization, UC realizability can be readily tested and arrays of UC's can be synthesized to realize arbitrary Boolean functions.

In this paper the problems associated with the minimal realization of synchronous sequential machines by unate cellular cascades have been studied. Given the sequential machine in the form of a flow table, a systematic procedure is followed to generate all the selectable sets. Compatible sets consisting of these selectable sets are next determined and the different secondary variables are assigned. The nested functional forms of the next-state expressions for these variables are finally established. The proposed method is very systematic and perfectly suited for machine processing.

The necessary and sufficient conditions for the linear realizability of a sequential machine are stated. The discussion considers the state transition and output functions separately and thus machines with nonlinear output function can also be tested for linearity of the state transition function. It then goes on to determine the characterizing matrices and corresponding secondary state assignment when such realization exists. The method can be applied to both permutation and nonpermutation machines.

In this paper, the concept of primary partition of Boolean functions has been introduced. A systematic method of obtaining the multithreshold realization of Boolean functions based on this new concept is presented. The problem essentially reduces to a table lookup procedure; the computational labor in finding the minimum-threshold minimum fan-in solution is substantially reduced.

A simple method for the implementation of Booth's algorithm for multiplication of signed binary numbers has been presented. It has been shown that for large word lengths, a significant economy has been achieved compared to Majithia and Kitai's method.

A permuter network is used to arbitrarily change the ordering of the variables of a switching function. A new scheme for permuter arrays is discussed in this note whereby the variables are selected sequentially by a number of "selector cells" according to the required output ordering. A cellular realization of the selector cell is suggested.

A simple algorithm for testing the 2-summability of Boolean functions is presented in this note. The concept of asummobility has been extended and the idea of "mutual 2-asummability" has been introduced. The authors show how mutual 2-asummobility can be utilized for the testing of isobaricity of threshold functions containing no more than seven variables.

Any switching function can always be realized by a single multithreshold threshold element possessing a suitable number of thresholds. However, the practical realization of such elements often presents serious difficulties; as such it becomes more convenient to realize the given function in the form of a network of multi-threshold threshold elements, each possessing fewer thresholds. In this paper, a thorough study of these networks with different modes of interconnection has been made. These discussions have been limited to constant weight (CW) networks only. Finally, a technique for obtaining the three-threshold network configuration for an arbitrary k-threshold function has also been suggested. It has been assumed that feedback loops are absent.

The irredundant prime closed sets play an important role in the simplification of an incompletely specified flow table. In this note, an algebraic method for deriving the irredundant prime closed sets corresponding to any given flow table has been presented. It has been shown that the complete set of irredundant prime closed sets is obtained following the procedure suggested.

In the present paper efforts have been made to arrive at the three-level NAND network of any general Boolean function by utilizing its complementary function. It has been shown that the knowledge of the complementing gates of the three-level NAND circuit with minimum number of gates in the AND level can readily be obtained from the study of the prime implicants of the complementary function. A reduced form of the Cover and Closure (CC) table is suggested which is applicable in the above three-level NAND network synthesis. The paper also deals with the recognition of the class of functions for which the use of the CC table may be avoided to obtain the same network.

A decomposition and reconstruction approach for synthesizing an arbitrary Boolean function with a minimum number of threshold logic elements connected by feedforward paths only is presented. Attention is mainly focused on cascade-type realizations. The approach has the advantage that near-minimal solutions are readily derived. An estimate of how closely the minimality has been approached is obtainable in this method. The method has been successfully applied by the authors to Boolean functions of 5 and 6 variables.

In this short note, an attempt has been made to arrive at a general algorithm for minimizing the number of internal states in an incompletely specified flow table. The closure property of the compatibility classes which cover a given flow table leads us to the derivation of a particular class of closed sets defined as irredundant prime closed sets. It has been shown that these prime closed sets in sequential circuit synthesis play an analogous role to that of the prime implicants in combinational circuit synthesis. A method has been described for determining all the irredundant prime closed sets and finding the minimal row flow table by suitably choosing one or a collection of those sets.

One of the basic problems of combinational switching circuit theory is that of designing circuits with a minimum number of AND-gates or prime implicants. Algorithms have been formulated for this purpose which first generate all possible prime implicants corresponding to a specified switching function and then select minimal subsets of these prime implicants for use in the formation of the minimal networks [1]-[6]. In practically all the currently available methods of simplification of switching functions, use is made of the minterm type expression specified in the algebraic or its equivalent binary or decimal form. Operations with binary or decimal numbers have become very popular because of their inherent advantages.