We propose a framework to quickly analyze track congestion inside each g-cell at the global routing stage. A distinguishing feature of our framework compared to prior work is estimating the locations of vias and partial track utilization by a global segment inside each g-cell for a given global routing solution. We integrate this model with a proposed track assignment algorithm which we show can more effectively reduce track overlaps compared to prior work. A strength of this work is to evaluate the accuracy with respect to an accurate congestion map generated by a commercial detailed router as reference. This work is a step towards bridging the gap between global and detailed routing which is an important obstacle facing modern IC design.

We study the impact of using 3D monolithic (3DM) standard cells on improving detailed routability and pin access. We propose a design flow which transforms standard rows of single-tier "2D" cells into rows of standard 3DM cells folded into two tiers. The transformation preserves layout characteristics such as overall area and number of metal layers for signal routing (i.e., M2 and above). It also creates redundant pins and free routing tracks in the two tiers used by the 3DM cells. We then propose an Integer Linear Program which routes as many nets as possible on the free 3DM routing tracks, leaving the rest of the nets to be routed via a standard global and detailed router on the metal layers dedicated for signal routing. Our experiments show significant improvement in detailed routability metrics using 3DM cells compared to using 2D standard cells.

This paper proposes global routing models for capturing the impact of local congestion caused by varying-size vias. The models are then incorporated to dynamically drive a proposed layer assignment algorithm. A typical characteristic of advanced technology nodes is significantly high variation in wire sizes that may exist between adjacent metal layers. Routing from a global cell (g-cell) to its top metal layer results in using a via which may be up to twice the size of unit wire track within that g-cell. This results in significant decrease in the available routing tracks that could pass the boundaries of the g-cell. Ignoring this issue hampers the effectiveness of traditional global routing algorithms due to mismatch with the detailed routing stage. Based on these observations, we propose “via-aware edge overflow” and “edge-aware via overflow” models for capturing the impact of both unstacked and stacked vias of arbitrary sizes during global routing. Our models can be used to drive any layer assignment algorithm and replace the traditional edge overflow and via overflow metrics. To show the impact of our models, we also incorporate them in a proposed two-stage layer assignment algorithm and compare with a competitive layer assignment technique. This is also the first work to actually evaluate the impact of global routing solutions using a commercial detailed router. In our experiments we report fewer number of design rule check violations by only changing the layer assignment during global routing, and detail routing with Olympus-SoC of Mentor Graphics.

Split manufacturing is a technique that allows manufacturing the transistor-level and lower metal layers of an integrated circuit (IC) at a high-end, untrusted foundry, while manufacturing only the higher metal layers at a smaller, trusted foundry. Using split manufacturing is only viable if the untrusted foundry cannot reverse engineer the higher metal layer connections (and thus the overall IC design) from the lower layers. This paper studies the effectiveness of proximity attack as a key step to reverse engineer a design at the untrusted foundry. We propose and study different proximity attacks based on how a set of candidates are defined for each broken connection. The attacks use both placement and routing information along with factors which capture the router's behavior such as per-layer routing congestion. Our studies are based on designs having millions of nets routed across nine metal layers and significant layer-by-layer wire size variation. Our results show that a common, Hamming distance-based proximity attack seldom achieves a match rate over 5%. But our proposed attack yields a relatively small list of candidates which often contains the correct match. Finally, we propose a procedure to artificially insert routing blockages in a design at a desired split level, without causing any area overhead, in order to trick the router to make proximity-based reverse engineering significantly more challenging.

This work is the first to present global routing models for capturing the impact of local congestion caused by varying-size vias. The models are then incorporated to dynamically drive a proposed layer assignment algorithm. A typical characteristic of advanced technology nodes is significantly-high variation in wire sizes that may exist between adjacent metal layers. Routing from a global cell (g-cell) to its top metal layer results in using a via which may be up to twice the size of unit wire track within that g-cell. This results in significant decrease in the available routing tracks that could pass the boundaries of the g-cell. Ignoring this issue hampers the effectiveness of traditional global routing algorithms due to acting as, now, a significant source of mismatch with the detailed routing stage. Based on these observations, we propose “via-aware edge overflow” and “edge-aware via overflow” models for capturing the impact of both unstacked and stacked vias of arbitrary sizes during global routing. Our models can be used to drive any layer assignment algorithm and replace the traditional edge overflow and via overflow metrics. To show the impact of our models, we also incorporate them in a proposed two-stage layer assignment algorithm and compare with a competitive layer assignment technique. This is also the first work to actually evaluate the impact of global routing solutions using a commercial detailed router. In our experiments we report less number of DRC violations by only changing the layer assignment at global routing, and detailed route using the Olympus-SoC of Mentor Graphics.

Split manufacturing is a technique that allows manufacturing the transistor-level and lower metal layers of an IC at a high-end, untrusted foundry, while manufacturing only the higher metal layers at a smaller, trusted foundry. Using split manufacturing is only viable if the untrusted foundry cannot reverse engineer the higher metal layer connections (and thus the overall IC design) from the lower layers. This work studies the effectiveness of proximity attack as a key step to reverse engineer a design at the untrusted foundry. We propose and study different proximity attacks based on how a set of candidates are defined for each broken connection. The attacks use both placement and routing information along with factors which capture the router's behavior such as per-layer routing congestion. Our studies are based on designs having millions of nets routed across 9 metal layers and significant layer-by-layer wire size variation. Our results show that a common, Hamming Distance-based proximity attack seldom achieves a match rate over 5%. But our proposed attack yields a relatively-small list of candidates which often contains the correct match. Finally, we propose a procedure to artificially insert routing blockages in a design at a desired split level, without causing any area overhead, in order to trick the router to make proximity-based reverse engineering significantly more challenging.