In this work, we elaborate on our endeavors to design, implement, fabricate, and post-silicon validate CoFHEE 1, a co-processor for low-level polynomial operations targeting Fully Homomorphic Encryption execution. With a compact design area of 12mm2, CoFHEE features ASIC implementations of fundamental polynomial operations, including polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which underlie most higher-level FHE primitives. CoFHEE is capable of natively supporting polynomial degrees of up to n = 214 with a coefficient size of 128 bits, and has been fabricated and silicon-verified using 55nm CMOS technology. To evaluate it, we conduct performance and power experiments on our chip, and compare it to state-of-the-art software implementations and other ASIC designs.

In this paper, we present the blueprint of a specialized co-processor for Fully Homomorphic Encryption, dubbed CoFHEE. With a small design area of$12mm^{2}$, CoFHEE incorporates ASIC implementations of fundamental polynomial operations, such as polynomial addition and subtraction, Hadamard product, and Number Theoretic Transform, which are underneath all higher-level FHE primitives. CoFHEE has native support of polynomial degrees of up to$n=2^{14}$with a coefficient size of 128 bits. We evaluate our chip with performance and power experiments and compare it against state-of-the-art software implementations and other ASIC designs. A more elaborate description of the CoFHEE design can be found in [1].

This paper presents a 120 GHz receiver for Near-Field IoT sensors, without the conventional LNA and mixers building blocks. A new technique for the reduction of the low-frequency 1/f noise is also presented. The technique is used to improve the sensitivity of the 120GHz receiver with a data rate of 100kb/s, by lowering the 1/f noise corner frequency. The technique involves the complementary switching of two MOSFET transistors in order to effectively act as a single MOSFET transistor. It also involves the isolation of the drain terminals of these identical MOSFET transistors in order to eliminate any electric field from the complementary transistors which may affect the de-trapping process. The complementary switching in the literature has only been applied to low-frequency circuits with the highest operating frequency being 120 kHz. The proposed technique leads to a 9dB reduction in the drain current noise at frequencies up to 100 kHz. Realized in a 65nm CMOS LPE technology from GlobalFoundries™, the receiver has a measured sensitivity of −46dBm, power consumption of$\mathbf{52}\ \boldsymbol{\mu} \mathbf{W}$, and energy efficiency of 5.2pJ/bit. The occupied on-chip area is 0.56mm2.

This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.

A tunable 10-stage all-pole (Papoulis) low-pass filter occupying 0.1815mm2 is designed and integrated as a building block in a 22nm CMOS FDSOI receiver for the 5G. Each filter stage comprises of a two-stage unity gain buffer with common mode feedback loop. Tunable resistors between each stage determine the bandwidth of the filter in the range of 0.7 GHz to 1.5 GHz. An identical filter structure, but with the outputs fed back to the inputs functions as an oscillator. Correlating the oscillation frequency with the filter bandwidth, under the same tuning conditions, the filter bandwidth can be calibrated to account for PVT variations. Measurement results show an in-band OIP3 of 8.8dBm and a nearly linear phase response at a power consumption of 35mW to 50mW from a 1V supply. The power/pole of 3.3mW/GHz is the best when compared to other filters from literature.

A CMOS broadband 1:4 active power divider is proposed in this paper. The power splitter can be used in Phased Array Transceivers at the Transmitter side. It is based on a cascode 1:4 current splitter and transmission lines. Compared to other passive power dividers and active power dividers, the proposed design exhibits 1-2 dB power gain and smaller area. The measured input 1dB compression point is 6 dB whereas the IIP3 is 7.2 dBm. The Noise Figure of the Power Divider is 10 dB at lower frequencies and 15 dB at 28 GHz. The measured results are performed across several chips. Realized in 22nm CMOS FDSOI from GF, the total power consumption is 29 mW from a 1 V power supply and the area occupied by the divider is 700μm × 600μm. A thorough analysis of the gain and noise of the divider is presented as well.

The paper proposes a receiver frontend operating at 64Gb/s with a bandwidth of 50GHz and transimpedance gain of 70dBH. It consists of a burst-mode transimpedance amplifier (TIA) distributed feedback voltage amplifiers and two offset control mechanisms. By using negative and positive feedback, the gain is decoupled from bandwidth. Realized in a 65nm CMOS LPE technology, the occupied real estate on chip is 2mm2. The measurement results show operation at 64Gb/s with PAM4 signals and NRZ signals.

A 28GHz, Modified Doherty Power Amplifier (MDPA) was implemented in 22nm FDSOI CMOS technology from GF. The MDPA adopts an asymmetrical topology utilizing two cascode CMOS amplifiers as the main (Class-A) and auxiliary (Class-C). This allows a supply voltage of 2.5V and consequently higher output power. The use of a main Class-A amplifier is conducive to a higher linearity (IIP3). The integrated design implements the main and auxiliary amplifier, along with the matching and transmission line networks on chip. The fabricated amplifier occupies an area of 1.2mm2, exhibits 12 dBm saturated output power, a peak power gain of 10dB, 16% peak power-added efficiency (PAE) and 12.5% at 6-dB back-off. The measured IIP3 is 20dBm.

This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the conventional DLDO design that targets μA load current. The RLC-DLDO consists of RLC, PMOS power switches and control unit. The RLC compares between the reference and the load voltage and generates a single bit that turns on/off the PMOS switches. Unlike the clocked comparator, the RLC is an event-driven design that continuously responds to the voltage difference. The control unit provides digital bits to control the power switches and the RLC circuit in order to support different output voltage levels. The RLC-DLDO has an input voltage range between 0.8V and 0.6V and generates an output voltage range between 0.7V to 0.5V for load current between 10μA and 500μA. The design is implemented in 22nm FDSOI and occupies an active area of 0.0171mm2. The simulation results show that the peak efficiency is 99.9% and the load transient response time is 5ns at VL=0.5V.

A differential T/H amplifier with a built in digital AGC function is realized in GF 65nm bulk CMOS LPE technology. The design consists of a linearized OTA at the input stage with a linear range of 800mVpp, diff followed by a super source follower and an output buffer. The T/H achieves a loss of -1.16dB in low gain mode and 0.6dB of gain in high gain mode. The circuit consumes 13.8mW at 1.2V supply and occupies an area of 0.109mm2. It achieves an ENOB of 8-9 and 8-12.7 fJ/conversion at 2.5GS/s.

This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.

In this paper, we propose mm-Waves for Near-Field IoT, ultralow power transceivers. With small footprint and no external components, the transceivers could be integrated with the sensors, with the wireless sensor nodes organized in a Master-Slave, asymmetrical network. With low complexity and high energy efficiency, the slave nodes benefit from a minimalist design approach with integrated antennas and integrated resonators for absolute frequency accuracy. Two designs are presented. The first is a K-band, super-regenerative, logarithmic-mode, OOK receiver achieving a peak energy efficiency of 200pJ/bit at 4Mb/s and a BER of 10−3. With 800μW peak and 8μW average power, the sensitivity of the receiver is −60dBm for the same data and bit-error rates. Realized in a 65nm CMOS process from GF, the active area of the receiver is 740×670μm2. The second design is a 100Kb/s, V-band transceiver with integrated antenna. It achieves 20pJ/bit energy efficiency (Rx mode) and it provides means for 1/f noise mitigation.

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in low-noise amplifiers, mixers and oscillators are considered. The concepts derived are applied to a few classes of wireless communications standards that are broadband in nature at RF and/or require a broadband IF. Multi-mode, multi-band operation and adaptability as key requirements for future generation receivers are highlighted throughout the paper.