Caroline A. Ross

dblp:177/9415 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2017
0000-0003-2262-1249ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 67% Memory systems · 33%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
beyond-CMOS computing
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
Emerging computing paradigms › neuromorphic computing
cognitive computing
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
Memory systems › processing-in-memory
logic-in-memory
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
Emerging computing paradigms
neuromorphic computing
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
Emerging computing paradigms › approximate and stochastic computing
probabilistic computing
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
Memory systems › emerging memory technologies
spintronic memory
0.312017
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited · DAC 2017
YearPublicationVenuePosition
2017 A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited
abstract
Many key technologies of our society, including so-called artificial intelligence (AI) and big data, have been enabled by the invention of transistor and its ever-decreasing size and ever-increasing integration at a large scale. However, conventional technologies are confronted with a clear scaling limit. Many recently proposed advanced transistor concepts are also facing an uphill battle in the lab because of necessary performance tradeoffs and limited scaling potential. We argue for a new pathway that could enable exponential scaling for multiple generations. This pathway involves layering multiple technologies that enable new functions beyond those available from conventional and newly proposed transistors. The key principles for this new pathway have been demonstrated through an interdisciplinary team effort at C-SPIN (a STARnet center), where systems designers, device builders, materials scientists and physicists have all worked under one umbrella to overcome key technology barriers. This paper reviews several successful outcomes from this effort on topics such as the spin memory, logic-in-memory, cognitive computing, stochastic and probabilistic computing and reconfigurable information processing.
Jianping Wang 0006, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy 0001, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
DAC13
2016 Cell-Based Design Methods for Directed Self-Assembly
abstract
Topographic templates can direct the self-assembly of block copolymers to achieve nanoscale patterns with high order. Previously, we have demonstrated well-aligned periodic lines, bends, and meshes using a sparse array of lithographically defined posts [1,2]. However, it is generally challenging to fabricate complex and non-periodic patterns using a sparse post array because the key information contained in the final pattern must be encoded in the sparse template. In this work, we present two cell-based design methods for fabricating complex patterns using directed self-assembly of polystyrene-b-polydimethylsiloxane (PS-b-PDMS) block copolymer thin films. For the first approach, we developed a set of template tiles consisting of square post lattices with a restricted range of geometric features. For all possible tile arrangements, we examined the resulting block copolymer patterns. We were able to predict a relatively simple template that will result in a desired complex pattern by combining tiles in different ways. For the second approach, we designed a binary-state system with ladder-shaped block copolymer structures using a square confinement. We developed design-rules for controlling alignment direction of the ladder-shaped structures by introducing openings around the square cells. These methods could provide a new template design method for a complex non-trivial block copolymer patterns.
Karl K. Berggren, Caroline A. Ross, Hyung Wan Do, Jae-Byum Chang, Hong Kyoon Choi
ISPD2