VLDB 2026 Research / reviewers in the wild / expert
Furkan Ercan
dblp:178/3822
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10ranked-venue papers
5as first author
6since 2021 · last 2023
0000-0003-0599-1766ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 7 · 4 first-author · 4 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | GRAND-EDGE: A Universal, Jamming-Resilient Algorithm with Error-and-Erasure DecodingabstractRandom jammers that overpower transmitted signals are a practical concern for many wireless communication protocols. As such, wireless receivers must be able to cope with standard channel noise and jamming (intentional or unintentional). To address this challenge, we propose a novel method to augment the resilience of the recent family of universal error-correcting GRAND algorithms. This method, called Erasure Decoding by Gaussian Elimination (EDGE), impacts the syndrome check block and is applicable to any variant of GRAND. We show that the proposed EDGE method naturally reverts to the original syndrome check function in the absence of erasures caused by jamming. We demonstrate this by implementing and evaluating GRAND-EDGE and ORBGRAND-EDGE. Simulation results, using a Random Linear Code (RLC) with a code rate of 105/128, show that the EDGE variants lower both the Block Error Rate (BLER) and the computational complexity by up to five order of magnitude compared to the original GRAND and ORBGRAND algorithms. We further compare ORBGRAND-EDGE to Ordered Statistics Decoding (OSD), and demonstrate an improvement of up to three orders of magnitude in the BLER. Furkan Ercan, Kevin Galligan, David Starobinski, Muriel Médard, Ken R. Duffy, Rabia Tugce Yazicigil |
ICC | 1 |
| 2023 | Demo: Universal Soft-Detection Decoder with Ultra-Low Energy Consumption Using ORBGRANDabstractThis work presents an interactive real-time demonstration of the first-integrated universal soft-detection decoder with an ultra-low energy consumption of 0.76pJ/bit and the lowest power of 4.9mW using Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND) [1]. The chip has a reconfigurable code length of 32 to 256 bits. The chip’s universality is demonstrated by decoding multimedia messages using different codebooks through an interactive Graphics User Interface (GUI). It is shown that the chip’s performance is independent of the codebook used and dynamically adapts to the channel noise conditions where lower energy is consumed as the Signal-to-Noise Ratio (SNR) of the channel improves. Arslan Riaz, Zeynep Ece Kizilates, Alperen Yasar, Furkan Ercan, Wei An 0001, Kevin Galligan, Muriel Médard, Ken R. Duffy, Rabia Tugce Yazicigil |
WoWMoM | 4 |
| 2022 | Interleaved Noise Recycling using GRANDabstractNoise recycling is a recently proposed method that significantly enhances decoding performance when used for orthogonal channels impacted by correlated noise with only receiver side changes. In this paper, we establish that noise recycling can be applied in a single communication channel that is subject to temporally correlated noise by leveraging a standard matrix interleaver to create the effect of orthogonal channels. The proposed interleaved noise recycling technique works with any code, requires no sender-side alterations, and only minor changes to the receiver architecture. In a hard-detection scenario, we demonstrate noise recycling can enable an accurate estimate of continuous realization of noise without using any soft information, resulting in a gain of more than 2 dB in Block Error Rate (BLER). We use the first hardware implementation of Guessing Random Additive Noise Decoding (GRAND), a universal noise-centric decoder, to illustrate the advantages of noise recycling in hardware performance. At a correlation coefficient of 0.75, Eb/N0of 4 dB, a maximum of 36× decoding energy savings with a 12× reduction in latency is achieved using a BCH(127,113) code when GRAND is equipped with the proposed noise recycling. Arslan Riaz, Amit Solomon, Furkan Ercan, Muriel Médard, Rabia Tugce Yazicigil, Ken R. Duffy |
ICC | 3 |
| 2022 | High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRANDabstractUltrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAND) is a recently proposed maximum likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, ordered reliability bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gb/s for a code length of 128 at a target frame error rate (FER) of 10−7. Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRAND with ABandonment (GRANDAB), a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code (PC) (128, 105), the proposed ORBGRAND VLSI implementation has$49\times $higher average throughput,$32\times $times more energy efficiency, and$5\times $more area efficiency while maintaining similar decoding performance. Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |
| 2021 | High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRANDabstractGuessing Random Additive Noise Decoding (GRAND) is a recently proposed approximate Maximum Likelihood (ML) decoding technique that can decode any linear error-correcting block code. Ordered Reliability Bits GRAND (ORBGRAND) is a powerful variant of GRAND, which outperforms the original GRAND technique by generating error patterns in a specific order. Moreover, their simplicity at the algorithm level renders GRAND family a desirable candidate for applications that demand very high throughput. This work reports the first-ever hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gbps for a code length of 128 at an SNR of 10 dB. Moreover, the proposed hardware can be used to decode any code provided the length and rate constraints. Compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar (128,105) code, the proposed VLSI implementation has 49× more average throughput while maintaining similar decoding performance. Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross |
ICASSP | 3 |
| 2021 | Fast SC-Flip Decoding of Polar Codes with Reinforcement LearningabstractIn this paper, we introduce a novel bit-flipping algorithm for fast successive cancellation (FSC) decoding of polar codes. In particular, we first propose a new bit-flipping strategy tailored to single parity-check (SPC) constituent codes of polar codes. A parameterized bit-flipping model is then developed and reinforcement learning (RL) is used to optimize the parameters. Our experimental results show that for a polar code of length 512 with 256 information bits, the proposed decoder has a better or similar error-correction performance compared to the state-of-the-art fast DSCF (FDSCF) decoding algorithm when the same number of maximum decoding attempts is considered. Nghia Doan, Seyyed Ali Hashemi, Furkan Ercan, Warren J. Gross |
ICC | 3 |
| 2020 | Simplified Dynamic SC-Flip Polar DecodingabstractSC-Flip (SCF) decoding is a low-complexity polar code decoding algorithm alternative to SC-List (SCL) algorithm with small list sizes. To achieve the performance of the SCL algorithm with large list sizes, the Dynamic SC-Flip (DSCF) algorithm was proposed. However, DSCF involves logarithmic and exponential computations that are not suitable for practical hardware implementations. In this work, we propose a simple approximation that replaces the transcendental computations of DSCF decoding. Moreover, we show how to incorporate fast decoding techniques with the DSCF algorithm. With proposed approaches, the computational complexity of DSCF decoding is remarkably reduced while maintaining equivalent decoding performance. Furkan Ercan, Thibaud Tonnellier, Nghia Doan, Warren J. Gross |
ICASSP | 1 |
| 2020 | Fast Thresholded SC-Flip Decoding of Polar CodesabstractSC-Flip (SCF) decoding algorithm shares the attention with the common polar code decoding approaches due to its low-complexity and improved error-correction performance. However, the inefficient criterion for locating the correct bit-flipping position in SCF decoding limits its improvements. Due to its improved bit-flipping criterion, Thresholded SCF (TSCF) decoding algorithm exhibits a superior error-correction performance and lower computational complexity than SCF decoding. However, the parameters of TSCF decoding depend on multiple channel and code parameters, and are obtained via Monte-Carlo simulations. Our main goal is to realize TSCF decoding as a practical polar decoder implementation. To this end, we first realize an approximated threshold value that is independent of the code parameters and precomputations. The proposed approximation has negligible error-correction performance degradation on the TSCF decoding. Then, we validate an alternative approach for forming a critical set that does not require precomputations, which also paves the way to the implementation of the Fast-TSCF decoder. Compared to the existing fast SCF implementations, the proposed Fast-TSCF decoder has 0.24 to 0.41 dB performance gain at frame error rate of 10-3, without any extra cost. Compared to the TSCF decoding, Fast-TSCF does not depend on precomputations and requires 87% fewer decoding steps. Finally, implementation results in TSMC 65nm CMOS technology show that the Fast-TSCF decoder is 20% and 82% more area-efficient than the state-of-the-art fast SCF and fast SC-List decoder architectures, respectively. Furkan Ercan, Warren J. Gross |
ICC | 1 |
| 2019 | Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar CodesabstractThe interest in polar codes has been increasing significantly since their adoption for use in the 5thgeneration wireless systems standard. Successive cancellation (SC) decoding algorithm has low implementation complexity, but yields mediocre error-correction performance at the code lengths of interest. SC-Flip algorithm improves the error-correction performance of SC by identifying possibly erroneous decisions made by SC and re-iterates after flipping one bit. It was recently shown that only a portion of bit-channels are most likely to be in error. In this paper, we investigate the average log-likelihood ratio (LLR) values and their distribution related to the erroneous bit-channels, and develop the Thresholded SC-Flip (TSCF) decoding algorithm. We also replace the LLR selection and sorting of SC-Flip with a comparator to reduce the implementation complexity. Simulation results demonstrate that for practical code lengths and a wide range of rates, TSCF shows negligible loss compared with the error-correction performance obtained when all single-errors are corrected. At matching maximum iterations, TSCF has an error-correction performance gain of up to 0.45 dB compared with SC-Flip decoding. At matching error-correction performance, the computational complexity of TSCF is reduced by up to 40% on average and requires up to 5× lower maximum number of iterations. Furkan Ercan, Carlo Condo, Warren J. Gross |
IEEE Trans. Commun. | 1 |
| 2018 | Partitioned Successive-Cancellation Flip Decoding of Polar CodesabstractPolar codes are a class of channel capacity achieving codes that has been selected for the next generation of wireless communication standards. Successive-cancellation (SC) is the first proposed decoding algorithm, suffering from mediocre errorcorrection performance at moderate code lengths. In order to improve the error-correction performance of SC, two approaches are available: (i) SC-List decoding which keeps a list of candidates by running a number of SC decoders in parallel, thus increasing the implementation complexity, and (ii) SC-Flip decoding that relies on a single SC module, and keeps the computational complexity close to SC. In this work, we propose the partitioned SC-Flip (PSCF) decoding algorithm, which outperforms SCFlip in terms of error-correction performance and average computational complexity, leading to higher throughput and reduced energy consumption per codeword. We also introduce a partitioning scheme that best suits our PSCF decoder. Simulation results show that at equivalent frame error rate, PSCF has up to 4.1× less computational complexity than the SC-Flip decoder. At equivalent average number of iterations, the error-correction performance of PSCF outperforms SC-Flip by up to 0.26 dB at frame error rate of 10-3. Furkan Ercan, Carlo Condo, Seyyed Ali Hashemi, Warren J. Gross |
ICC | 1 |