VLDB 2026 Research / reviewers in the wild / expert
Paul Budnik
dblp:178/3896
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1971
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 88% Parallel and multicore computing · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory interference
memory bank conflicts |
0.0 | 1 | 1971 | The Organization and Use of Parallel Memories · IEEE Trans. Computers 1971 |
Memory systems › memory architecture
parallel memory organization |
0.0 | 1 | 1971 | The Organization and Use of Parallel Memories · IEEE Trans. Computers 1971 |
Memory systems
memory access latency |
0.0 | 1 | 1971 | The Organization and Use of Parallel Memories · IEEE Trans. Computers 1971 |
Parallel and multicore computing › parallel architecture
parallel processor design |
0.0 | 1 | 1971 | The Organization and Use of Parallel Memories · IEEE Trans. Computers 1971 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1971 | The Organization and Use of Parallel MemoriesabstractAs computer CPUs get faster, primary memories tend to be organized in parallel banks. The fastest machines now being developed can fetch of the order of 100 words in parallel. Unless memory and compiler designers are careful, serious memory conflicts and resulting performance degradation may result. Some of the important questions of design and use of such memories are discussed. Paul Budnik, Davis J. Kuck |
IEEE Trans. Computers | 1 |