A sequential machine that processes its inputs without changing state can be represented as a constrained combinational network. A system of Boolean equations that represent such a network must include assertions that formalize the required constraints. These constraints can be expressed as assertions about certain gate inputs and certain gate outputs within the network. In such networks, redundant and partially redundant gates are not pathological. The fault analysis method presented provides for the testing of both sides of an irredundant gate and for the detectable side of a partially redundant gate.