The investigation of multiprocessor architectures and parallel algorithms for speech recognition is important. Large vocabulary speech recognition is a computationally intensive problem, which can require orders of magnitude acceleration over uniprocessors to achieve real-time performance. Also, there is still much algorithm development work to be done, which requires a programmable computer rather than a hardware implementation. This paper describes a massively parallel hardware/software architecture that is applicable to accelerating a wide class of large vocabulary speech recognition algorithms. The general principles of applicability supporting this claim will be described. Timing and sizing results obtained by applying these principles to Rabiner's level-building DTW algorithm for connected-word recognition will be given. Finally, a benchmark algorithm is described that demonstrates the programmability and performance of the architecture.

Two techniques are described for efficient encoding of features in pattern recognition. It is shown that the number of binary digits needed to represent patterns can be greatly reduced using efficient feature encoding. Four-thousand utterances based on a 40-word vocabulary are used to evaluate the techniques.