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F. P. Maison

dblp:178/3977 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1971
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
fault-tolerant architecture
0.011971
The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process · IEEE Trans. Computers 1971
Hardware reliability and fault tolerance › redundancy
modular redundancy
0.011971
The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process · IEEE Trans. Computers 1971
Hardware reliability and fault tolerance
redundancy
0.011971
The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process · IEEE Trans. Computers 1971
Processor architecture and microarchitecture › microprogramming
microprogrammed architecture
0.011971
The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

random redundancy · 0.0hamming code · 0.0gate connector redundancy · 0.0duplex redundancy · 0.0
YearPublicationVenuePosition
1971 The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process
abstract
A self-reconfigurable and fault-tolerant computer has been realized in Electronique Marcel Dassault Laboratories in France. It is a microprogrammed character-coded computer using a READ-WRITE microprogram memory. A special Hamming code is used for character encoding. The arithmetic operators are table operators mounted in a duplex scheme. Logical operators use gate connector redudancy. Counters and registers use random redundancy, i.e., any spare part, selected in a waiting list, can replace any failed part having the same function. These different parts of the computer, their design criteria, and the computer architecture are described in detail. The computer needs about three times more components than a conventional computer.
F. P. Maison
IEEE Trans. Computers1