Demo Data from VLDB 2026 / reviewers in the wild / expert
Terry G. Gaddess
dblp:178/6121
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1970
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 50% Integrated circuit design · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
arithmetic circuit design |
0.0 | 1 | 1970 | An Error-Detecting Binary Adder: A Hardware-Shared Implementation · IEEE Trans. Computers 1970 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1970 | An Error-Detecting Binary Adder: A Hardware-Shared Implementation · IEEE Trans. Computers 1970 |
Hardware reliability and fault tolerance
error detection and correction |
0.0 | 1 | 1970 | An Error-Detecting Binary Adder: A Hardware-Shared Implementation · IEEE Trans. Computers 1970 |
Hardware reliability and fault tolerance › arithmetic codes
residue codes |
0.0 | 1 | 1970 | An Error-Detecting Binary Adder: A Hardware-Shared Implementation · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
self-checking circuits · 0.0residue code · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1970 | An Error-Detecting Binary Adder: A Hardware-Shared ImplementationabstractA design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry. Terry G. Gaddess |
IEEE Trans. Computers | 1 |