Demo Data from VLDB 2026 / reviewers in the wild / expert
John B. Connolly
dblp:179/4918
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1967
0000-0002-7033-3463ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 54% Electronic design automation · 40% Interconnection networks and networks-on-chip · 6% |
Topics — the 4 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
fault masking |
0.0 | 1 | 1967 | Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems · IEEE Trans. Electron. Comput. 1967 |
Hardware reliability and fault tolerance › redundancy
redundant logic |
0.0 | 1 | 1967 | Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems · IEEE Trans. Electron. Comput. 1967 |
Electronic design automation › signal integrity
crosstalk |
0.0 | 1 | 1966 | Cross Coupling in High Speed Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Electronic design automation
signal integrity |
0.0 | 1 | 1966 | Cross Coupling in High Speed Digital Systems · IEEE Trans. Electron. Comput. 1966 |
Methods — techniques the papers use, named apart from their topics
von neumann redundancy · 0.0transmission line analysis · 0.0duplication · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1967 | Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking SystemsabstractThis paper describes a logical redundancy technique based on failure-erasure circuitry that is capable of automatically masking as many as P-1 individual failures in P identical elements connected in parallel. This technique is contrasted with the standard von Neumann scheme where only (P/2) such failures can be tolerated. In order to prevent the effect of any single failure from propagating, each logical element in the original network need only be duplicated rather than triplicated as in the von Neumann technique. The usefulness of the redundancy technique described is predicated on the existence of circuitry that fails to a NULL state rather than to a ZERO or ONE state. Accordingly, several circuits which exhibit the desired failure mode and that are worthy of further development for reliability applications are discussed. John B. Connolly, William G. Schmidt |
IEEE Trans. Electron. Comput. | 1 |
| 1966 | Cross Coupling in High Speed Digital SystemsabstractIt is now well understood that the design of the signal distribution systems of high speed digital machines is as important as the design of the circuits themselves. The integrated circuit technology of today is pressing back the frontiers of speed and simultaneously providing more circuitry per unit area. A signal distribution system with suitable electrical characteristics for these high speed circuits and which is physically compatible with the circuit size is sorely needed. A candidate for such an application is the multilayer board. This paper considers the problem of cross coupling from line to line in multilayer when the excitation function is a fast rise time voltage pulse. Curves and equations are given which enable the design of a system with a given system characteristic impedance and a specified cross-coupling ratio. Experimentally obtained wave shapes from single ground plane transmission lines are given, and a practical numerical example is worked. John B. Connolly |
IEEE Trans. Electron. Comput. | 1 |