An integrated BCD gate driver employing adaptive dead-time control (ADTC) and a compact gate-boost (GB) circuit is presented. The ADTC reduces both dead-time intervals from conventional$\sim 10 ~\text{ns}$to a nearly load-independent high-to-low dead time$\left(D T_{F}\right)$of$0.7-1.2 ~\text{ns}$over$1-6 ~\mathrm{A}$, and digitally minimizes low-to-high dead time ($D T_{R}$) to$\sim 1 ~\text{ns}$, lowering bodydiode conduction and reverse-recovery losses. At$38 ~\mathrm{V}, 6 ~\mathrm{A}$, and 2.2 MHz, this recovers a combined dead-time loss of up to 1.47 W, yielding an efficiency gain of 1.81 %. In addition, the open-loop GB circuit accelerates the later stage of the high-side transition, halving the$L X$rise time (28.4 ns to 14.5 ns) and yielding an additional 1.09 W loss reduction and 1.33 % efficiency gain. Overall, the proposed solution achieves a total loss reduction of 2.56 W and a 3.14 % absolute efficiency improvement.

A high-speed, low-figure-of-merit capacitive floating level shifter (CF-LS) for high-side bootstrapped gate drivers is presented. The design integrates a feedback discharge control (FBDC) for enhanced$V {_{\text {SW}}}$dV/dt (SRSW) immunity and combines a mismatch reduction circuit (MMRC) with a common-mode blanking pulse (CMBP) to block common-mode (CM) signals with mismatch. Fabricated in a 0.75-$\mu $m STMicroelectronics bipolar-CMOS-DMOS (BCD) process, the proposed CF-LS occupies 0.048 mm2with the core area being 0.026 mm2, making it highly compact and integration-friendly. It achieves a propagation delay ($T {_{\text {P}}}$) of 1.525 ns and transition energy ($E_{T}$) of 29.77 pJ at 40 V, both of which remain approximately constant across the$V {_{\text {SW}}}$sweep from 0 to 40 V, while maintaining measured SRSWimmunity of up to 20 V/ns and mismatch tolerance up to 30%. Compared to recent works, the design offers a$2\times $improvement in figure-of-merit2 (FoM2), achieving 2.68 ns$\cdot $pJ/$\mu $m${^{{3}}} \cdot $V at bootstrap supply ($V {_{\text {BS}}}$) of 5 V, and$3\times $improvement when supplied at 3.3 V. The CF-LS has been comprehensively validated both as a standalone circuit and when integrated within a dc–dc buck converter, making it a highly robust, efficient, and versatile solution for high-frequency power management systems operating up to 55 MHz.

A high-speed low-figure-of-merit capacitive-coupled level shifter tailored for high-side bootstrapped gate drivers is presented. Key techniques include a Feedback Discharge Control (FBDC) for improved dV/dt Immunity, a MisMatch Reduction Circuit (MMRC) in combination with Common-Mode Blanking Pulse (CMBP) to block common-mode signals with improved mismatch tolerance. The level shifter is fabricated in a 0.75µm STMicroelectronics BCD process and covers a chip area of 0.048mm2. Experimental results demonstrate a Propagation delay (TP) of 1.525ns and Transition Energy (ET) of 29.77pJ at 40V, with a dV/dt immunity of up to 20V/ns. The level shifter achieves a figure-of-merit 2 (FoM2) of 2.68ns.pJ/um3.V, an improvement of 2x from the recent literature, and exhibits a mismatch tolerance of 20%. The design has been tested at a switching frequency (FSW) of up to 55MHz. The design is validated through standalone and integrated testing in a DC-DC buck converter.

This paper presents a monolithic GaN current sense circuit designed for the high-side of a 100-V half-bridge. The circuit is engineered to minimize current offsets and response times across a wide range of input voltages (10 V to 100 V), as well as varying temperatures and current loads. It is capable of tracking inductor current ripples and detecting the zero-current condition of the half-bridge high-side power transistor. The proposed solution demonstrates a simulated loop gain exceeding 100 dB and a bandwidth of 43.9 MHz, which achieves an accuracy of 99.4% and a response time of 145 ns under operating conditions of 50-V input voltage, 10-A current load, and 27°C.