In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Drain-induced barrier lowering (DIBL) and the variation in DIBL are found to exhibit a logarithmic dependence with drain bias in the advanced node FinFET devices. Correctly capturing the DIBL and device variation as a function of drain bias is required, as the SRAM operation voltage range is expanded. We show the improved hardware correlation in Vmin yield and the improved slow corner read performance when the Vds-dependent variation is considered.

A previously unrecognized vertical-extrinsic device in advanced 7-nm FinFET SRAM structures is identified and characterized for the first time. The ON-current for this vertical-extrinsic device is modulated by gate bias and exhibits a process-dependent threshold behavior. The ON-state of this parasitic device can exceed several nanoamperes and become the dominant mechanism in the static power of an SRAM array. Aggressively pushed ground rules used to achieve competitive SRAM density can result in exposure in FinFET-based SRAMs to this parasitic leakage path; n-Well and p-well dopant profiles, alignments, and dimensions must be carefully controlled to avoid this leakage mechanism in high-density FinFET SRAM arrays.

Traditional techniques for statistical analysis of rare events require a good understanding of the dependence of the outputs on the independent input variables. This can sometimes be an insurmountable challenge, especially when the dimensionality of the input variation space is high. In this paper, we present an innovative scaled sigma sampling (SSS) technique that is able to obtain an accurate quantification of the low probability tails without requiring visibility to the failure regions or their input dimensionality. SSS leverages the probability density differences produced by process sigma scale factors to uncover the nature of the population redistribution induced by the circuit. This understanding is used to construct an efficient transform for the circuit metric, one that has the same sigma scale factor dependency of the cumulative probabilities as the SPICE simulations. This transform is then used to obtain the low probability tails corresponding to the original process distribution. We present representative circuit applications to illustrate the large savings in computational costs that one can achieve with SSS and the transparency and accuracy of this approach.

Spiraling costs of a product revision demand that we mitigate risks to product yield due to unintended disconnects between SPICE models used for design and production silicon, and intentional process retargeting for product performance optimization. This often necessitates product robustness to about +/-4.0-sigmas or about 60 ppm. However, the computational costs of even the most advanced simulation techniques are so prohibitive for many of the large circuit design problems that one often cannot obtain visibility to circuit behavior below about 5000 ppm. In this paper, we build on the scaled sigma sampling (SSS) foundation presented earlier and develop a formalism for efficient assessment of circuit yield exposure to low probability tails, including estimation of its confidence interval and optimization of process sigma scale factors and sample sizes used for the SPICE simulations. We illustrate the efficacy of SSS through an extended suite of circuit yield estimation examples including one that investigates the yield dependencies of a normality capable metric on process shifts and multiplicity.