This paper presents a 6.8-GHz compact digital fractional-N PLL based on a pulse-shaped loop filter, enabling a loop bandwidth of$0.26f_{ref}$to suppress the ring oscillator’s phase noise. It leverages a constant-slope DTC with range extension technique to save 50% area of the capacitor array. The embedded nonlinearity cancellation and digital offset compensation further improve the spectrum purity. Fabricated in a 28-nm CMOS process, the pulse-shaper-based PLL occupies$\text {0.025mm}^{{2}}$core area, achieves an integrated jitter of 804 fs and −53.2 dBc fractional spur at near-integer channels with a power consumption of 5.68mW, obtaining a$\text {FoM}_{\text {Jitter-N-Area}}$of −269.9 dB.

This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.

This article presents a 26–32-GHz 6-bit bidirectional passive vector modulation phase shifter (PVM-PS) in 40-nm CMOS for phased array systems. The passive phase shifter comprises a center-tap transformer-based quadrature generator/combiner, two 6-bit X-type attenuators, and a differential Wilkinson power combiner/divider. The symmetric design enables bidirectional signal propagation and offers flexible system configuration. Passive switches are sized to optimize the tradeoff among gain variation, insertion loss, and linearity. The phase shifter implemented in 40 nm covers a range of 360° with 5.625° resolution and the rms phase error is between 0.4° and 1.3°. It exhibits <1-dB magnitude imbalance and <1.2° phase imbalance between forward and reverse propagation modes. Its OP1dB is above −1 dBm across the operation frequency.

This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog converter (C-DAC) to adjust the initial voltage of the discharging process, the DTC achieves a fine resolution of$\mu \text{W}$at 50-MHz clock rate. It achieves a fine resolution of 563-fs over a 10-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.14/0.96-LSB, respectively.

This paper presents an analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided, followed by practical design guide that achieves the optimum spur/jitter trade-off. The proposed sub-sampling phase detector incorporates an active primary-secondary architecture for improved isolation to suppress the load modulation. The adaptive frequency locked loop (FLL) consumes zero power in the locked state and activates itself once unlocking is detected. The sub-sampling PLL is fabricated in a 40nm CMOS process. It achieves -121.5dBc/Hz phase noise at 1MHz offset frequency and an RMS jitter of 185fs integrated from 10k to 10MHz. The power dissipation is 1.14mW at 0.95V supply with a -254.1dB figure-of-merit. The proposed phase detector results in -73dBc reference spur that is among the lowest in state-of-art works.

This paper presents a wideband 6-12GHz two-stage low noise amplifier (LNA) that utilizes capacitor assisting triple-winding transformer in the inter-stage matching network. The electric coupling introduced by the assisting capacitor expands the design space by allowing independent control of each effective coupling strength of the three coupled inductors. The equivalent negative resistor enhanced by this capacitor improves the quality factor of the inter-stage network at high frequencies, which further improves the overall design trade-off among gain, bandwidth and noise figure. Fabricated in a 130nm SOI CMOS process, the LNA achieves a remarkable 0.8-1.5dB NF,$< $-14dB S11,$< $-8dB S22, -11.8dBm IP$_{\mathbf{1dB}}$and 21.8-23.3dB power gain across the 6-12GHz passband with ±0.75dB ripple while drawing 20mA from a 3.3V supply.

This article introduces a highly integrated passive wireless sensing system based on the extended electronic product code (EPC) Gen2 protocol, using sensor tags and a reader to support concurrent data streams from multiple sensors. Multiple subcarrier multiple access (MSMA) is used by assigning different subcarrier frequencies to the sensor tags for backscattering so that each tag has an independent channel for communication to achieve the simultaneous streaming of multisensor data. In order to improve the subcarrier frequency accuracy and further increase the number of communication channels, this article proposes a novel method of subcarrier frequency calibration based on the Gen2 protocol. This method enables a high-accuracy clock to be generated on-chip. At the same time, this article also proposes a method based on Gen2 protocol to start a group of tags and receive real-time data in parallel. The tag chip is fabricated in a$0.18{-}\mu \text{m}$CMOS process with a die size of$850\,\,\mu \text{m}\,\,\times 850\,\,\mu \text{m}$, and the reader prototype is built using software-defined radio equipment. The test results show that the sensing system proposed in this article can collect and recognize concurrent data streams from multiple sensor tags synchronously. The measured sensitivity of the sensor tag is −14.9 dBm with a 3-axis accelerating sensor, and the calibration accuracy of subcarrier frequency is better than${\pm }{\mathrm {0.385}}$kHz in the range of 40–640 kHz. With this accuracy, the tags can be allocated up to 78 subcarrier communication channels theoretically.

In this paper, the analysis and design of a 57-64 CMOS Power Amplifier is discussed. The power-combining technique and the capacitor neutralization technique are applied to boost the performance of the purposed PA. The PA is designed in 65nm bulk CMOS process to achieve a saturated output power of 19.4dBm and a peak power-added efficiency of 22%. The power amplifier consumes 300mW from a 1.2V power supply at the output-refereed 1dB compression point of 16.1dBm, and the corresponding power-added efficiency is 13.0%. The passive devices, such as the transformers, the power-combiner and the pads, are designed by Electromagnetic Field Simulation on ADS momentum.

A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd‐order active‐RC filter is designed with current‐efficient feedforward compensated OTA. And a digital‐to‐time converter (DTC) assisted fractional‐N all‐digital phase‐locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. The presented receiver is fabricated in 55 nm CMOS technology with an active area of 2.3 mm2 and power consumption of 20 mW. Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out‐of‐band IIP3 is +8 dBm, and in‐band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in‐band PN and −120.5 dBc/Hz at 1 MHz offset.

This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma‐delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the 1/f3 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

A low-noise triple band transmitter for GSM triple-band and WCDMA is presented. By programming parameters, analog baseband and RF frontend can handle signals of different protocols and frequency bands. Novel linearization method is used in LPF and driver amplifier to meet the demand of 3G systems. Noise optimization is also adopted so that our transmitter achieves −157 dBc/Hz noise at 190 MHz frequency offset in WCDMA band, which eliminates external SAW filter.