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Noriyoshi Yoshida

dblp:18/247 · DBLP profile ↗
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21ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 13Theory of computation · 5Software engineering, systems software and programming languages · 2Databases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Graph algorithms and graph theory · 50% Algorithms and data structures · 50%
Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 99% Integrated circuit design · 1%

Topics — the 12 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Algorithms and data structures › recursive algorithms
divide-and-conquer
0.112007
A Deterministic Algorithm for Finding All Minimum k-Way Cuts · SIAM J. Comput. 2007
Graph algorithms and graph theory › graph cut
minimum k-cut
0.112007
A Deterministic Algorithm for Finding All Minimum k-Way Cuts · SIAM J. Comput. 2007
Electronic design automation
physical design
0.021996
Pin assignment with global routing for VLSI building block layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › physical design › routing
global routing
0.011996
Pin assignment with global routing for VLSI building block layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › physical design › floorplanning
pin assignment
0.011996
Pin assignment with global routing for VLSI building block layout · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › physical design › placement
gate assignment
0.011987
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › physical design
placement
0.011987
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Data models and query languages › conceptual modeling
semantic data model
0.011984
A Semantic Approach to Usability in Relational Database Systems · ICDE 1984
Electronic design automation › high-level synthesis
scheduling
0.011989
A Meeting Scheduler for Office Automation · IEEE Trans. Software Eng. 1989
Data models and query languages
query language design
0.011984
A Semantic Approach to Usability in Relational Database Systems · ICDE 1984
Electronic design automation
circuit synthesis
0.011973
A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits · Inf. Control. 1973
Integrated circuit design
digital circuit design
0.011973
A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits · Inf. Control. 1973

Methods — techniques the papers use, named apart from their topics

divide-and-conquer · 0.1linear time optimal channel pin assignment · 0.0scheduling algorithm · 0.0heuristic algorithm · 0.0semantic data modeling · 0.0linear algebra over finite fields · 0.0
YearPublicationVenuePosition
2007 A Deterministic Algorithm for Finding All Minimum k-Way Cuts
abstract
Let $G=(V,E)$ be an edge‐weighted undirected graph with n vertices and m edges. We present a deterministic algorithm to compute a minimum k‐way cut of G for a given k. Our algorithm is a divide‐and‐conquer method based on a procedure that reduces an instance of the minimum k‐way cut problem to $O(n^{2k-5})$ instances of the minimum $(\lfloor (k+\sqrt{k})/2\rfloor+1)$‐way cut problem, and can be implemented to run in $O(n^{4k/(1-1.71/\sqrt{k}) -31} )$ time. With a slight modification, the algorithm can find all minimum k‐way cuts in $O(n^{4k/(1-1.71/\sqrt{k}) -16} )$ time.
Yoko Kamidoi, Noriyoshi Yoshida, Hiroshi Nagamochi
SIAM J. Comput.2
2002 A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida
FPL4
2002 A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem
Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
Algorithmica3
1997 A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs
Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
Integr.5
1996 A three-layer over-the-cell multi-channel router for a new cell model
Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
Integr.4
1996 Pin assignment with global routing for VLSI building block layout
abstract
In this paper, we will consider global routing and pin assignment in VLSI building block layout, and present an efficient algorithm which integrates global routing, pin assignment, block reshaping and positioning. The general flow of the proposed algorithm is the same as the one proposed in by Cong in 1991 [1] and consists of two main phases. The first phase is to determine not only global routes and coarse pin assignment in the same way as [1], but also shapes and positions of blocks. The second phase is to compute the final pin assignment for channels. We generalize the channel pin assignment (CPA) problem in [1], in which the CPA problem is formulated for only channels formed by two blocks, to the CPA problem for channels formed by multiple blocks. We will propose a linear time optimal channel pin assignment algorithm, which is an extension of the algorithm in [1]. Experimental results show the effectiveness of the proposed algorithm.
Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1995 A new system partitioning method under performance and physical constraints for multi-chip modules
abstract
No abstract available.
Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
ASP-DAC4
1995 A three-layer over-cell multi-channel routing method for a new cell model
abstract
No abstract available.
Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
ASP-DAC4
1995 An MCM Routing Algorithm Considering Crosstalk
abstract
This paper presents an MCM routing algorithm considering crosstalk. The aim of the algorithm is to minimize the total wire length under the condition that the crosstalk constraints among nets are satisfied. Experimental results show the effectiveness of the algorithm.
Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
ISCAS4
1995 A Verification Algorithm for Logic Circuits with Internal Variables
abstract
In this paper, we present a formal verification method based on internal variables of a given circuit. In this method, the problem of deciding the logical equivalence of two logic circuits is transformed to the satisfiability problem, which is solved by constructing a set of BDDs, each of which is corresponding to an internal variable of the circuit. Experimental results showed the effectiveness of the proposed method.
Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
ISCAS4
1994 On Three-Way Graph Partitioning
abstract
Given an undirected graph G with n vertices, m edges and positive edge weights and k terminals {s/sub 1/, s/sub 2/, ..., s/sub k/} on G, the problem of computing a minimum k-way cut of G is to find a minimum (cost) k-way cut C that disconnects each terminal from all the others. The minimum k-way cut problem is known as NP-hard even if all vertex degrees are three or less and k is equal to 3. The minimum k-way cut problem for a planar graph and fixed integer k can be solved in polynomial time. This paper presents an algorithm for computing a minimum three-way cut of a graph in a larger class than planar graphs.>
Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
ISCAS3
1994 A Floorplanning Method with Topological Constraint Manipulation
abstract
In this paper, we propose a heuristic floorplanning method. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method reduces the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results showed that the quality of solutions of the proposed method is good and even for the large number of blocks, the proposed method keeps a high quality of solution.>
Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
ISCAS5
1994 A Systolic Graph Partitioning Algorithm for VLSI Design
abstract
The graph partitioning problem is to partition the vertices of an undirected graph G=(V, E) into two sets of equal size such that the number of edges between them is minimized. In this paper, we propose a systolic algorithm for graph partitioning. The algorithm is based on the Kernighan-Lin heuristic algorithm, runs on a linear array consisting of O(|V|) processing units, and is very suitable for direct VLSI implementation. Computation time of one pass of the proposed algorithm is O(|V|). Simulation experiments showed that the proposed algorithm is as good as the original KL heuristic.>
Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
ISCAS4
1993 Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints
Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
ISCAS5
1989 A Meeting Scheduler for Office Automation
abstract
Scheduling of meetings is one of the basic functions demanded in office automation, since office workers spend much time on meetings. This paper discusses a schedufkng problem of meetings and presents a meeting scheduler for office automation which provides an automatic mechanism for updating a schedule of meetings.
Kazuo Sugihara, Tohru Kikuno, Noriyoshi Yoshida
IEEE Trans. Software Eng.3
1987 A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach
abstract
In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.
Takashi Fujii, Hideya Horikawa, Tohru Kikuno, Noriyoshi Yoshida
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
1984 A Semantic Approach to Usability in Relational Database Systems
abstract
This paper attempts to design a user-friendly interface which enhances usability of relational database systems. Our approach to usability is to design a semantic data model suitable for a user interface and provide an easy-to-use query language DOMCALC (domain calculus language) which is based on the semantic data model. A query in DOMCALC can be described in terms of intuitive notions, namely domains, instead of relations and attributes. That is, DOMCALC requires for users no knowledge of a conceptual database such as relation names and attribute names. Therefore, the usability based on the semantic data model removes the requirement of knowledge of a conceptual database from users and protects user views from changes in the conceptual database. We also describe an outline of a database system PRIM (Prototype of Laboratory information Management System) which has been developed with the above considerations. This is a step toward the enhancement of usability in relational database systems.
Kazuo Sugihara, Jun'ichi Miyao, Tohru Kikuno, Noriyoshi Yoshida
ICDE4
1983 A linear algorithm for the domination number of a series-parallel graph
Tohru Kikuno, Noriyoshi Yoshida, Yoshiaki Kakuda
Discret. Appl. Math.2
1980 NP-completeness of some type of p-center problem
Tohru Kikuno, Noriyoshi Yoshida, Yoshiaki Kakuda
Discret. Appl. Math.2
1979 A fast selective traversal algorithm for binary search trees
abstract
The process of visiting a mini mal number of nodes to retrieve data satisfying the range condition from a binary search tree is called "selective traversal". Driscall and Lien gave an algorithm SELECT for selective traversal which used a MARKER field of 3 bits for each node in the tree. In this paper we present a new algorithm, called INPROC, which uses a MARKER field of 2 bits and runs faster than algorithm SELECT.
Tohru Kikuno, Noriyoshi Yoshida, Hiromi Kusumoto
COMPSAC2
1973 A Method of Synthesis and Decomposition of Autonomous Linear Sequential Circuits
Tadashi Ae, Noriyoshi Yoshida
Inf. Control.2