Demo Data from VLDB 2026 / reviewers in the wild / expert
Chi-Jiunn Jou
dblp:18/3094
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 67% Interconnection networks and networks-on-chip · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
analytical modeling |
0.0 | 1 | 1987 | Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems · IEEE Trans. Computers 1987 |
Performance modeling and evaluation › queueing models
blocking probability |
0.0 | 1 | 1987 | Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems · IEEE Trans. Computers 1987 |
Interconnection networks and networks-on-chip › bus-based interconnection
multiple bus network |
0.0 | 1 | 1987 | Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems · IEEE Trans. Computers 1987 |
Methods — techniques the papers use, named apart from their topics
queueing analysis · 0.0analytical modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus SystemsabstractThis correspondence presents two expressions in calculating effective memory bandwidth for a wide range of multiple-bus configurations. Also presented is an analytical solution for determining each processor's blocking probability in a multiple-bus system where different priorities are assigned to the processors. Chi-Jiunn Jou |
IEEE Trans. Computers | 2 |