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Atsushi Sugiyama

dblp:18/3655 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Processor architecture and microarchitecture · 13%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification		 0.011986
An extensive logic simulation method of very large scale computer design · DAC 1986
Electronic design automation › hardware verification and test
logic simulation		 0.011986
An extensive logic simulation method of very large scale computer design · DAC 1986
Processor architecture and microarchitecture › general-purpose processor architecture
mainframe processor design		 0.011986
An extensive logic simulation method of very large scale computer design · DAC 1986

Methods — techniques the papers use, named apart from their topics

multi-level simulation · 0.0function test programs · 0.0
YearPublicationVenuePosition
1986 An extensive logic simulation method of very large scale computer design
abstract
The paper describes one of the methods to evaluate the design verification progress of logic simulation. In the development of the very large scale general purpose computer HITACHI M-680H/682H, the function test programs designed for the products have been directly used to verify the design in simulation. Test programs establish the definite goal and enable to extensively verify the design. The simulation techniques, which carry out at high speed the very large design described in different levels of abstraction, have developed for this purpose. The method has detected 30% of design errors of M-68X and effectively reduced its development time.
Masayuki Miyoshi, Yoshio Ooshima, Atsushi Sugiyama, Nobuhiko Onizuka, Nobutaka Amano
 DAC3
1986 DVTS: Design Verification Techniques for Functional Simulation
Kohei Fukuoka, Ken Ohga, Atsushi Sugiyama, Satoshi Takemura
 ITC3