Demo Data from VLDB 2026 / reviewers in the wild / expert
James Phillips
dblp:18/4933
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2017
0000-0002-0996-3036ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 76% Integrated circuit design · 24% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 2 | 1994 | High-Performance 3-1 Interlock Collapsing ALU's · IEEE Trans. Computers 1994 Interlock Collapsing ALU's · IEEE Trans. Computers 1993 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit |
0.0 | 1 | 1993 | Interlock Collapsing ALU's · IEEE Trans. Computers 1993 |
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design |
0.0 | 1 | 1994 | High-Performance 3-1 Interlock Collapsing ALU's · IEEE Trans. Computers 1994 |
Integrated circuit design
digital arithmetic circuits |
0.0 | 1 | 1994 | High-Performance 3-1 Interlock Collapsing ALU's · IEEE Trans. Computers 1994 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1993 | Interlock Collapsing ALU's · IEEE Trans. Computers 1993 |
Methods — techniques the papers use, named apart from their topics
CMOS · 0.0carry-save adder · 0.0carry-lookahead adder · 0.03-1 ALU design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | A Conceptual Measurement Model for eHealth Readiness: a Team Based Perspective
James Phillips, Simon K. Poon, Mary K. Lam, Monique Hines, Melissa Brunner, Emma Power, Melanie Keep, Tim Shaw, Leanne Togher |
AMIA | 1 |
| 1994 | High-Performance 3-1 Interlock Collapsing ALU'sabstractA high-performance 3-1 interlock collapsing ALU, i.e., an ALU that allows the execution of most execution interlocks in a single machine cycle, is presented. We focus on reducing the Boolean equations describing the device and the incorporation of new mechanisms in the interlock collapsing ALU design. In particular, we focus on the reduction of the critical path, regarding delay, for the interlock collapsing ALU implementation. It is shown that the delay associated with the implementation of the proposed device, in terms of logic stages, assuming a commonly available CMOS technology, is equivalent to the number of logic stages required for the implementation of a 3-1 binary adder. The resulting implementation demonstrates that the proposed 3-1 interlock collapsing ALU can be designed to outperform existing schemes for interlock collapsing ALU's by a factor of at least two. Finally, it is suggested that the proposed device can be used in the implementation of multiple instruction issuing machines, allowing the issuance and execution of interlocks in parallel and in a single machine cycle with no cycle time increases.> James Phillips, Stamatis Vassiliadis |
IEEE Trans. Computers | 1 |
| 1993 | Interlock Collapsing ALU'sabstractA device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two's complement, unsigned binary, and binary logical operations. It is shown that status for ALU operations using a 3-1 ALU can be determined in a parallel fashion, resulting in the compliance of the proposed device with predetermined architectural behavior of single instruction execution. The device requires no more logic stages than does a 3-1 binary adder using a carry-save adder (CSA) followed by a carry-lookahead adder (CLA) design. Design considerations using a commonly available CMOS technology are also reported, indicating that the device will not increase the machine cycle of an implementation. It is suggested that the device can maintain full architectural compatibility.> Stamatis Vassiliadis, James Phillips, Bart Blaner |
IEEE Trans. Computers | 2 |