This paper describes the theory and design of digital high-radix multiplier-dividers (Patent Pending). The theory of high-radix division is extended to high-radix multiplier-dividers that can perform fused multiplication and division operations using a single recurrence relation. With the fused implementation of multiplication and division, the two operations can be executed using a single instruction, implying only a single rounding operation. The recurrence relation is described, the quotient digit selection function derived, and important design parameters together with their optimal values and relations are defined. Efficient design procedure and implementation hardware are described and important system parameter values for various radix systems computed. Compared to pure dividers, the multiplier-divider requires a slightly more complex data path and quotient digit selection function.

This paper studies the effect of high performance pipelined GF(2256) bit-serial multiplier on elliptic curve point operations. A 3-stage pipelined version of the Massy-Omura GF(2m) normal basis multiplier for 160 lesm les 256 was studied in terms of area overhead and throughput improvement. Simple gate area and delay models were used to estimate the throughput of the pipelined and the non-pipelined multipliers. The proposed pipelined architecture has been shown to have a significant improvement in throughput allowing a single 3-stage pipelined multiplier to have higher throughput than an architecture employing three parallel non-pipelined multipliers. The AT2performance metric has shown an even more significant improvement.

This paper presents an efficient high performance elliptic curve scalar multiplication method with resistance against Timing Attacks. The main idea of the proposed method is to control the main scalar multiplication loop such that- either- a- single-point- addition' is- performed- or- a- number- of- consecutive point doublings that take the same time taken by a single point addition is- performed. The proposed method works with both binary-encoded as well as NAF-encodedprivate keys with NAF encoding yielding higher performance. It requires no extra fake computations and its time complexity is less than other recently reported countermeasures, especially when parallel multipliers are used.

A new technology mapper (SELF-Map) for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.