Sequences of events, such as crashes in the stock market or outages in a network, contain strong temporal dependencies, whose understanding is crucial to react to and influence future events. In this paper, we study the problem of discovering the underlying causal structure from event sequences. To this end, we introduce a new causal model, where individual events of the cause trigger events of the effect with dynamic delays. We show that in contrast to existing methods based on Granger causality, our model is identifiable for both instant and delayed effects. We base our approach on the Algorithmic Markov Condition, by which we identify the true causal network as the one that minimizes the Kolmogorov complexity. As the Kolmogorov complexity is not computable, we instantiate our model using Minimum Description Length and show that the resulting score identifies the causal direction. To discover causal graphs, we introduce the Cascade algorithm, which adds edges in topological order. Extensive evaluation shows that Cascade outperforms existing methods in settings with instantaneous effects, noise, and multiple colliders, and discovers insightful causal graphs on real-world data.

In this article, we propose a highly reliable transmission strategy based on exploiting channel diversity for Internet of Things (IoT) networks equipped with cognitive radio (CR) capabilities (referred to as CR-IoT networks). Specifically, we investigate the channel-assignment problem with the objective of minimizing the number of assigned channels for each CR transmission subject to link reliability, data rate, and success probability constraints. We use the theory of continuous-time Markov chains to derive mathematical expressions for channel availability and reliability. These expressions are employed in a binary linear program model to formulate the channel assignment optimization problem, which is suboptimally solved using a polynomial-time sequential fixing procedure. Theoretical performance analysis of the proposed channel assignment scheme is derived in terms of a lower bound on the achievable probability of successful packet transmission. Through simulation experiments, we demonstrate significant performance enhancement compared to existing reliability-unaware CR channel assignment algorithms.

Summary Spectrum sharing protocols for cognitive radio networks (CRNs) are often designed based on an exclusive channel occupancy policy. This policy does not allow concurrent cognitive radio (CR) transmissions to take place over the same channel. Unfortunately, this can significantly affect spectrum utilization and network performance. Allowing several secondary users to simultaneously share the same channel naturally improves spectrum utilization and avoids unnecessary blocking of CR transmissions. The key challenge in enabling efficient operation of multichannel CRNs is how to perform efficient power‐controlled media‐access‐control (MAC) protocols. These protocols include both power control and channel assignment. In this paper, we propose a power‐controlled MAC protocol for CRNs based on interference‐channel occupancy model with the objective of maximizing the number of served CR transmissions. It uses a novel power‐controlled channel assignment mechanism that allows several concurrent interference‐limited transmissions to simultaneously proceed over each idle channel in the same neighborhood. We present two variants of the power‐controlled channel assignment mechanism. The first proposed variant is suitable for CRNs with fixed data packet size, whereas the other is suitable for dynamic CRNs with variable packet size. The second variant of our protocol employs a users' scheduling procedure that attempts to fully utilize the available time‐frequency blocks. Simulation results indicate that employing transmission power control along with appropriate channel assignment and users' scheduling in CRNs can significantly improve the spectrum utilization and the overall network performance.

A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation is presented in this paper to replace both the external frequency reference and PLL combination used in current wearable medical devices. The system uses one loop to stabilize the amplitude and the other to stabilize the slope of a saw-tooth signal to generate stable frequency over a wide range. Measurement results from a chip fabricated in 180nm CMOS process gives a linear frequency range of 0.1MHz-10MHz and 7us settling time without using a PLL. The total power consumption is 360uW that includes output buffers and external current sources with ±0.84% variation in frequency from 0-70 degrees. Using the proposed system as a clock generator for microcontrollers used in current wearable medical devices, would result in a one or more order of magnitude reduction in power consumption.

This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2resulting in the best performance-area trade-off system presented up-to-date.

This paper presents an area-efficient frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique for software-defined radios. A background calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous quadrature frequency coverage, while only occupies a small area of 0.38 mm2and consumes 16-26 mW depending on output frequency, from a 1.2 V power supply. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7 GHz carrier frequency.

This paper presents a 60-GHz direct-conversion transceiver in 65 nm CMOS technology. By the proposed gain peaking technique, this transceiver realizes good gain flatness and is capable of more than 7 Gbps in 16QAM wireless communication for all channels of IEEE802.11ad standard within EVM of around -23 dB. The transceiver consumes 319mWin transmitting and 223mW in receiving, including the PLL consumption.

A 58.1-to-65.0 GHz frequency synthesizer using sub-harmonic injection-locking technique is presented. The synthesizer can generate all 60GHz channels defined by IEEE 802.15.3c, wirelessHD, IEEE 802.11ad, WiGig, and ECMA-387. A frequency calibration scheme is proposed to monitor frequency shift resulting from environmental variations. Implemented in a 65nm CMOS process, the synthesizer achieves a typical phase noise of -117 dBc/Hz @10MHz offset from a carrier frequency of 61.56 GHz.

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The 65 nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in a package are 8 Gbps in QPSK mode and 11 Gbps in 16QAM mode within a BER of-3. The transceiver consumes 186 mW while transmitting, and 106 mW while receiving. The PLL also consumes 66 mW.

This paper proposes Progressive Mixing Injection Locked Frequency Divider (PMILFD) technique that enhances the locking range for higher division ratios. As this technique uses lower and much stronger harmonics in the mixing process, it results in a stronger injection effect and a much wider locking range. Two 20GHz PMILFDs were designed based on this approach to divide by 4 and 8 using a 65nm CMOS process. The former achieves a 7.9GHz(31.4%) locking range and the later achieves a 3.4GHz(15.5%) while consuming 3.9mW and 7.1mW, respectively.

This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results show a phase noise of -96dBc/Hz at 60GHz while consuming 77.5mW from a 1.2V supply.