Deep neural network (DNN)-based methodologies have shown impressive performance and robustness in the detection of abnormalities and decoding of multi-modal biosignals. While the use of DNNs provides promising classification and decoding capabilities, it also introduces significant design and cost challenges for the implementation of biomedical System on Chips (SoC). To address the increasing demand for advanced and efficient DNN-based healthcare solutions at the edge, we propose BioSeek, an agile design generation framework enhanced by cutting-edge large-language models (LLM). BioSeek offers a comprehensive solution to the design challenges associated with biosignal processors. The effectiveness of BioSeek is evaluated through the design generation of both application-specific and versatile biosignal processors, demonstrating performance that is competitive with existing solutions.

Recently, advances in neuroscience and the rise of artificial intelligence have significantly enhanced the capabilities of epilepsy diagnosis. While EEG-based diagnosis offer a promising avenue for detecting and predicting seizure activity, practical implementation in real-world scenarios remains hindered by the heterogeneity of epilepsy and the variability of patient-specific biomarkers over time. Conventional deep learning models, trained on historical EEG, often fail to adapt to such biomarker variations, leading to degraded performance. Moreover, the computational and memory constraints of edge devices further exacerbate the challenge of on-device learning. To address these challenges, we introduce a novel framework, Memory-Efficient Intrinsic Gating Adaptation (MEIGA), designed to enhance real-world epilepsy diagnosis on resource-constrained edge devices. Our approach pre-trains a model using historical EEG data and employs lightweight adapter networks for efficient on-device tuning across new sessions, addressing session-to-session variability. By leveraging Direct Feedback Alignment (DFA), MEIGA reduces memory usage and computational overhead while maintaining high classification accuracy. Extensive experiments on the CHB-MIT epilepsy dataset demonstrate that MEIGA outperforms the pretrained-only Vision Transformer baseline, raising seizure prediction accuracy from 47.88% to 86.77% with only 3,908 tunable parameters (5.05% of the backbone). For seizure detection, MEIGA improves accuracy from 85.06% to 96.29% by adapting 2,008 parameters (17.40% of the base architecture). Further experiments on the AES dataset demonstrate that MEIGA consistently delivers strong performance across subjects and scales effectively to larger networks.

Deep learning associated with neurological signals is poised to drive major advancements in diverse fields such as medical diagnostics, neurorehabilitation, and brain-computer interfaces. The challenge in harnessing the full potential of these signals lies in the dependency on extensive, high-quality annotated data, which is often scarce and expensive to acquire, requiring specialized infrastructure and domain expertise. To address the appetite for data in deep learning, we present Neuro-BERT, a self-supervised pre-training framework of neurological signals based on masked autoencoding in the Fourier domain. The intuition behind our approach is simple: frequency and phase distribution of neurological signals can reveal intricate neurological activities. We propose a novel pre-training task dubbed Fourier Inversion Prediction (FIP), which randomly masks out a portion of the input signal and then predicts the missing information using the Fourier inversion theorem. Pre-trained models can be potentially used for various downstream tasks such as sleep stage classification and gesture recognition. Unlike contrastive-based methods, which strongly rely on carefully hand-crafted augmentations and siamese structure, our approach works reasonably well with a simple transformer encoder with no augmentation requirements. By evaluating our method on several benchmark datasets, we show that Neuro-BERT improves downstream neurological-related tasks by a large margin.

Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable the agile design of DCIM macros with optimal architectures, we present SynDCIM - a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. Testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.

Recent advancements in brain-computer interfaces (BCIs) and deep learning have made decoding lexical tones from intracranial recordings possible, providing the potential to restore the communication ability of speech-impaired tonal language speakers. However, data heterogeneity induced by both physiological and instrumental factors poses a significant challenge for unified invasive brain tone decoding. Particularly, the existing heterogeneous decoding paradigm (training subject-specific models with individual data) suffers from the intrinsic limitation that fails to learn generalized neural representations and leverages data across subjects. To this end, we introduce Homogeneity-Heterogeneity Disentangled Learning for Neural Representations (H2DiLR), a framework that disentangles and learns the homogeneity and heterogeneity from intracranial recordings of multiple subjects. To verify the effectiveness of H2DiLR, we collected stereoelectroencephalography (sEEG) from multiple participants reading Mandarin materials containing 407 syllables (covering nearly all Mandarin characters). Extensive experiments demonstrate that H2DiLR, as a unified decoding paradigm, outperforms the naive heterogeneous decoding paradigm by a large margin. We also empirically show that H2DiLR indeed captures homogeneity and heterogeneity during neural representation learning.

Over the past decade, artificial intelligence (AI) has made unprecedented advancements in various fields. However, with the emergence of large-scale models in recent years, the energy consumption associated with AI computing has become a critical issue that urgently needs to be addressed. Furthermore, as Moore's Law reaches its limits, increasing computational power has become extremely challenging. The scarcity of energy and computational resources presents significant challenges to the further development and application of current AI technologies. These challenges provide an unprecedented opportunity for the introduction of neuromorphic computing chips which show great potential in addressing the problems currently faced by AI. We present in this article the evolution of brain-inspired neuromorphic computing chips, tracing their evolution from the early artificial retina to advanced designs incorporating millions of artificial neurons. Also, we explore future opportunities in key applications such as brain-computer interfaces, which can facilitate more efficient neural communication; embodied intelligence, which seeks to replicate human cognitive functions; and large-scale models, where these chips' energy-efficient processing capabilities can greatly enhance AI system performance and scalability.

In this paper, we present a wireless closed-loop neuromodulation platform dedicated to diabetes management through implants in various body locations, such as the brain, stomach, and pancreas. The system's key components comprise a System-on-Chip (SoC) featuring a maximum 64-channel neural recording block to explore both neural roots and muscles involved in diabetes emergence and interactions within diverse organs with superior spatial resolution, an energy-efficient Impulse Radio Ultra-Wideband (IR-UWB) wireless transmitter, and an 8-channel stimulator for highly selective organ targeting. These capabilities are further enhanced by an edge-based Artificial Intelligence (AI) mechanism for real-time analysis. Simulation results show a total power consumption of 31.16 μW per channel for the recording and wireless transmission units, while the stimulator, powered by an inductive link, offers adjustable output with a maximum current of 3 mA and a voltage compliance of 9 V. Additionally, AI implemented as a four-layer neural network (NN) model using a field-programmable gate array (FPGA) on a wearable system achieved an accuracy of 98.06% in test sets.

Spiking transformers have been successfully applied to multiple applications with comparable accuracy with native transformers. Achieving a high energy efficiency with spiking transformers requires dedicated hardware design, especially a specialized matrix multiplication engine optimized for spike input. In this paper, we propose a carry-save adder (CSA) array with an improved energy and area efficiency for spiking transformer matrix multiplication computation. A two-staged CSA structure is proposed to support maximum logic reuse between 1b self-attention mode and 8b linear mode. Besides, a cubic-mesh architecture is proposed to organize CSA trees to reuse weight in different timesteps. Compared to a baseline accumulation design, the proposed architecture achieved a 2.7x area reduction and a 3.75x power reduction with the same throughput, showing that the optimized computation array has great potential to be applied in digital neuromorphic accelerators.

In the realm of implantable brain neural interfaces, a prominent challenge is the constraint of limited power, particularly in systems with a high channel count. Various generic and application-specific strategies have been proposed to enhance energy efficiency while preserving signal integrity, resulting in varying levels of effectiveness. We introduce in paper an innovative approach that employs an auxiliary bypass featuring a low-power, low-sampling-rate level-crossing analog-to-digital converter (LC-ADC) to exploit signal sparsity. This method facilitates adaptive power control of the core Successive Approximation Register analog-to-digital converter (SAR ADC), achieving a significant 65% reduction in power consumption compared to traditional high-precision SAR ADCs. The ADC is fabricated using a 40 nm technology node, providing a bandwidth range from 10 Hz to 1 MHz and attaining an effective number of bits (ENOB) reaching up to 10.56 bits, with a figure-of-merit (FoM) as low as 2.56 fJ/conversion. This advancement underscores the potential for enhanced energy efficiency in high-channel-count neural interfaces.

In this paper, we present a novel self-adaptive pseudo-resistor (A-PR) designed to enhance the performance of neurorecording front-end circuits in terms of settling time, linearity, and tunability. We validate the effectiveness of the proposed A-PR through the implementation of a capacitively- coupled instrumentation amplifier (CCIA) recording front-end using TSMC 40-nm process technology. The results demonstrate that the A-PR enables continuous recording with minimal interruptions, enhancing the system’s robustness and enabling more reliable acquisition of neural signals. Notably, the A-PR achieves a significant reduction in settling time, reaching the millisecond level—1000 times faster than conventional pseudo-resistors—while also exhibiting wide linear characteristics and easy tunability.

This paper presents a design of an eye tracking system based on neuromorphic computing to enhance user interaction in augmented reality (AR) and virtual reality (VR) environments. Traditional methods face challenges of high computational demands and power consumption. To address these issues, we propose a fully-spike eye-tracking system that utilizes dynamic vision sensors (DVS) for asynchronous pixel-level change detection, thereby reducing data redundancy and improving temporal resolution. We proposed a pipelined processor specifically tailored for handling DVS events and Spiking Neural Network (SNN) computations. Our spatial-temporal spike-streaming architecture enables cascaded computation across all layers, achieving high energy efficiency and high frame rate in eye-tracking tasks. Implemented in a 40nm CMOS process, NeuroEye demonstrates up to 12200 frame-per-second (FPS) and 4.47uJ/frame energy efficiency with 54.59mW power consumption in post-layout evaluations.

Electroencephalography (EEG)-based wearable brain-computer interfaces (BCIs) face challenges due to low signal-to-noise ratio (SNR) and non-stationary neural activity. We introduce in this manuscript a mathematically rigorous framework that combines data-driven noise interval evaluation with advanced SNR visualization to address these limitations. Analysis of the publicly available Eye-BCI multimodal dataset demonstrates the method’s ability to recover canonical P300 characteristics across frequency bands (delta: 0.5-4 Hz, theta: 4-7.5 Hz, broadband: 1-15 Hz), with precise spatiotemporal localization of both P3a (frontocentral) and P3b (parietal) subcomponents. To the best of our knowledge, this is the first study to systematically assess the impact of noise interval selection on EEG signal quality. Cross-session correlations for four different choices of noise intervals spanning from early to late pre-stimulus phases also indicate that alertness and task engagement states modulate noise interval sensitivity, suggesting broader applications for adaptive BCI systems. While validated in healthy participants, our results represent a first step towards providing clinicians with an interpretable tool for detecting neurophysiological abnormalities and provides quantifiable metrics for system optimization.

We investigated the fusion of the Intelligent Internet of Medical Things (IIoMT) with depression management, aiming to autonomously identify, monitor, and offer accurate advice without direct professional intervention. Addressing pivotal questions regarding IIoMT’s role in depression identification, its correlation with stress and anxiety, the impact of machine learning (ML) and deep learning (DL) on depressive disorders, and the challenges and potential prospects of integrating depression management with IIoMT, this research offers significant contributions. It integrates artificial intelligence (AI) and Internet of Things (IoT) paradigms to expand depression studies, highlighting data science modeling’s practical application for intelligent service delivery in real‐world settings, emphasizing the benefits of data science within IoT. Furthermore, it outlines an IIoMT architecture for gathering, analyzing, and preempting depressive disorders, employing advanced analytics to enhance application intelligence. The study also identifies current challenges, future research trajectories, and potential solutions within this domain, contributing to the scientific understanding and application of IIoMT in depression management. It evaluates 168 closely related articles from various databases, including Web of Science (WoS) and Google Scholar, after the rejection of repeated articles and books. The research shows that there is 48% growth in research articles, mainly focusing on symptoms, detection, and classification. Similarly, most research is being conducted in the United States of America, and the trend is increasing in other countries around the globe. These results suggest the essence of automated detection, monitoring, and suggestions for handling depression.

The Internet of Things (IoT) has become a transformative force across various sectors, including healthcare, offering new opportunities for automation and enhanced service delivery. The evolving architecture of the IoT presents significant challenges in establishing a comprehensive cyber‐physical framework. This paper reviews recent advancements in IoT‐driven healthcare automation, focussing on integrating technologies such as cloud computing, augmented reality and wearable devices. This work examines the IoT network architectures and platforms that support healthcare applications while addressing critical security and privacy issues, including specific threat models, attack classifications and security prerequisites relevant to the healthcare sector. This study highlights how emerging technologies like distributed intelligence, big data analytics and wearable devices are incorporated into healthcare to improve patient care and streamline medical operations. The findings reveal significant potential for IoT to transform healthcare practices, particularly in‐patient monitoring, and clinical decision‐making. However, security and privacy concerns continue to be a substantial barrier. The paper also explores the implications of global IoT and ehealth strategies and their influence on sustainable economic and community growth. It proposes an innovative cooperative security model to mitigate security risks in IoT‐enabled healthcare systems. Finally, it identifies key unresolved challenges and opportunities for future research in IoT‐based healthcare.

Vision Transformers (ViTs) have emerged as a dominant architecture in computer vision (CV), surpassing conventional neural network counterparts across diverse visual tasks. Despite their exceptional performance, ViTs incur substantial computational overhead characterized by high memory footprint, long inference latency, and elevated energy consumption. Current acceleration strategies for ViTs primarily focus on pruning operations or leveraging the inherent sparsity, requiring complex address control logic or position encoding. Alternatively, some software-based approaches attempt to pre-compute and separate dense and sparse matrix position encoding, while hardware solutions typically spend additional time and resources to obtain position encoding, decomposing matrix multiplications into structured forms. Through an analysis of ViTs’ parameters, we found that approximately 91.03% of the most significant bits (MSBs) are either 111s or 000s, and nearly 45% of 3 adjacent bits are identical. To leverage this characteristic of ViTs, we propose the Booth-Serial Skipping algorithm, which transforms the computation of consecutive 111 or 000 sequences into skip steps that require no additional computation time. Furthermore, the 4th to 6th bits of ViT weights can undergo aggressive scaling, enhancing the likelihood of Booth-skip operations with minimal impact on accuracy. The key innovation of this paper lies in exploiting the high proportion of naturally consecutive 0s or 1s in 8-bit weights during ViT inference and further expanding the skippable range through the Tunable Scaling strategy. At the hardware level, we develop a specialized accelerator to coordinate the proposed acceleration strategies. The processing element array in the accelerator is optimized for general matrix multiplication, it not only significantly improves the computation of multi-head self-attention but also enables resource reuse for linear transformations, ultimately optimizing end-to-end inference. Our design achieves$50.3\times $,$21.9\times $,$17.37\times $,$7.47\times $, and$1.49\times $an average end-to-end speedup on DeiT over CPU (Intel Xeon Gold 6152), EdgeGPU (NVIDIA Jetson Xavier NX), GPU (TITAN Xp), ViTCoD, and ViT-slice, respectively.

Visual prostheses are potential devices to restore vision for blind people, which highly depends on the quality of stimulation patterns of the implanted electrode array. However, existing processing frameworks prioritize the generation of stimulation while disregarding the potential impact of restoration effects and fail to assess the quality of the generated stimulation properly. In this paper, we propose for the first time an end-to-end visual prosthesis framework (StimuSEE) that generates stimulation patterns with proper quality verification using V1 neuron spike patterns as supervision. StimuSEE consists of a retinal network to predict the stimulation pattern, a phosphene model, and a primary vision system network (PVS-net) to simulate the signal processing from the retina to the visual cortex and predict the firing rate of V1 neurons. Experimental results show that the predicted stimulation shares similar patterns to the original scenes, whose different stimulus amplitudes contribute to a similar firing rate with normal cells. Numerically, the predicted firing rate and the recorded response of normal neurons achieve a Pearson correlation coefficient of 0.78.

The increasing interests in building bio-signal recording and processing systems for personal healthcare applications have been hindered by the critical sampling energy consumption issues of conventional biomedical systems. To address these limits, we propose a comprehensive strategy centered around a low-power level-crossing analog-to-spike converter (LC-ASC). This strategy enables event-driven compressive sampling by leveraging signal sparsity, achieving lower average sampling rates than Nyquist sampling. Our strategy includes universal VerilogA LC-ASC models, evaluation tools, and a reconfigurable data interface for versatile digital processing. Specifically, we introduce an online open-source VerilogA LC-ASC model and compression performance calculation tools for evaluating its performance with different bio-signals. The implemented LC-ASC chip demonstrates very-low power consumption of 31.5125.3 nW validated through chip measurements. Additionally, the proposed reconfigurable data interface ensures seamless integration with synchronous and asynchronous digital processing modules without sacrificing system-level performance. These advancements pave the way for energy-efficient neuromorphic biomedical circuits and systems.

On-chip learning of Spiking Neural Networks (SNN) has been extensively researched to enhance adaptability and privacy protection, with Back-Propagation-Through-Time (BPTT) emerging as the top-performing method despite its resourceintensive nature. In this paper, we propose a dedicated training processor that accelerates the BPTT algorithm for SNNs. We analyze the bottlenecks and optimization opportunities in SNN- BPTT and introduce novel techniques such as recalculation of membrane potentials to reduce redundant data movement. Additionally, we implement a pipeline architecture with heterogeneous computing cores to maximize hardware utilization and parallelism. Exploiting three types of sparsity in BPTT allows us to skip unnecessary computations and memory access, further optimizing performance. The proposed processor, implemented using 40nm CMOS technology, achieves simulation results with an advanced training energy efficiency of 0.86pJ/OP.

Precise bio-signal classification techniques for edge healthcare have been extensively researched, yet the scalability and efficiency of existing studies remain constrained by challenges in sensing, learning, and processing. Additionally, a deficiency in cross-level integration for the development of comprehensive healthcare systems has been observed. To tackle these issues and facilitate ultra-efficient personalized edge healthcare, this paper introduces the pioneering bionic sensor-direct on-chip learning and inference system with direct-feedback-through-time for user-specific cardiac arrhythmia detection, termed BOLS. This innovative system encompasses a compact sensor-direct feature extractor and a pipelined bionic processor, enabling end-to-end on-chip learning and inference. Employing cross-level co-design, our proposed bionic on-chip learning approach attains exceptional classification performance, boasting an accuracy of 98.6%, which ranks among the highest. The entire system has been implemented using 40nm CMOS process and subsequently verified. Remarkably, the proposed BOLS system consumes a mere 1.18mW for inference and 2.57mW for learning, resulting in an impressive power saving of over ×2000 compared to existing commercial training platforms.

Efficient design and optimization of flip-flops can significantly affect overall circuit performance as they have many applications in digital systems which can impact the overall power consumption and timings of the emerging system on chips (SOCs). In this paper, modeling, design, and optimization of transmission gate-based master-slave positive-edge-triggered flip-flop (TGFF) in 16 nm complementary metal-oxide semiconductor (CMOS) is proposed. The proposed deep neural network (DNN)-based optimization method first generates an accurate model for different performance metrics by using the training data obtained from transistor-level models which are over 100 times faster than them. Then, these accurate DNN-based models are used to optimize design goals such as dynamic and static power, setup time, and propagation delay (Data to Output). Using these fast, accurate models significantly speed up the design procedure and leads to a considerably more optimized design. Additionally, as the DNN is a universal approximator that can catch any nonlinear input-output relationship, the proposed method can be used to optimize circuits for any performance metric, even if no analytical formula is available. Additionally, circuit design based on the proposed method is automated which, facilitates the tasks of circuit designers.

Neuromorphic computing approaches such as Spiking Neural Networks (SNN) have been increasingly adopted in bio-signal processing and interpretation due to its intrinsic neurodynamic attribute. Nevertheless, reconciling performance and power efficiency in SNN implementation is still a bottleneck. Single-spike neural coding scheme, which is an extremely sparse coding scheme, provides a solution to bridge the gap. In this work, a neuromorphic architecture, using binary single spike neural signals, is proposed with both algorithm and hardware implementation. A sparsity-aware spatial-temporal back-propagation training method is proposed together with a single-spike coding scheme. Also, a novel neuromorphic accelerator is co-designed with algorithmic optimization and implemented in 40nm CMOS process. Experimental results show that the proposed processor reaches an accuracy of 94.61% on the MNIST dataset, 93.59% on the N-MNIST dataset, and 93.27% on the ECG dataset, respectively, while consumes$0.173\mu\mathrm{J}$per ECG classification task and 0.16mm2on-chip area. The overall power consumption is reduced by 91.68% compared to the state-of-the-art systems.

Intelligent and low-power retinal prostheses are highly demanded in this era, where wearable and implantable devices are used for numerous healthcare applications. In this paper, we propose an energy-efficient dynamic scenes processing framework (SpikeSEE) that combines a spike representation encoding technique and a bio-inspired spiking recurrent neural network (SRNN) model to achieve intelligent processing and extreme low-power computation for retinal prostheses. The spike representation encoding technique could interpret dynamic scenes with sparse spike trains, decreasing the data volume. The SRNN model, inspired by the human retina's special structure and spike processing method, is adopted to predict the response of ganglion cells to dynamic scenes. Experimental results show that the Pearson correlation coefficient of the proposed SRNN model achieves 0.93, which outperforms the state-of-the-art processing framework for retinal prostheses. Thanks to the spike representation and SRNN processing, the model can extract visual features in a multiplication-free fashion. The framework achieves 8 times power reduction compared with the convolutional recurrent neural network (CRNN) processing-based framework. Our proposed SpikeSEE predicts the response of ganglion cells more accurately with lower energy consumption, which alleviates the precision and power issues of retinal prostheses and provides a potential solution for wearable or implantable prostheses.

We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148$\boldsymbol {\mu }\mathbf {V_{rms}}$input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14${\mu }\text{V}$. Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost${\pm 2\pi }$input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

Wearable electrocardiograph (ECG) recording and processing systems have been developed to detect cardiac arrhythmia to help prevent heart attacks. Conventional wearable systems, however, suffer from high energy consumption at both circuit and system levels. To overcome the design challenges, this paper proposes an event-driven compressive ECG recording and neuromorphic processing system for cardiac arrhythmia detection. The proposed system achieves low power consumption and high arrhythmia detection accuracy via system level co-design with spike-based information representation. Event-driven level-crossing ADC (LC-ADC) is exploited in the recording system, which utilizes the sparsity of ECG signal to enable compressive recording and save ADC energy during the silent signal period. Meanwhile, the proposed spiking convolutional neural network (SCNN) based neuromorphic arrhythmia detection method is inherently compatible with the spike-based output of LC-ADC, hence realizing accurate detection and low energy consumption at system level. Simulation results show that the proposed system with 5-bit LC-ADC achieves 88.6% reduction of sampled data points compared with Nyquist sampling in the MIT-BIH dataset, and 93.59% arrhythmia detection accuracy with SCNN, demonstrating the compression ability of LC-ADC and the effectiveness of system level co-design with SCNN.

Real-time biosignal processing on wearable devices has attracted worldwide attention for its potential in healthcare applications. However, the requirement of low-area, low-power and high adaptability to different patients challenge conventional algorithms and hardware platforms. In this design, a compact online learning neuromorphic hardware architecture with ultralow power consumption designed explicitly for biosignal processing is proposed. A trace-based Spiking-Timing-Dependent-Plasticity (STDP) algorithm is applied to realize hardware-friendly online learning of a single-layer excitatory-inhibitory spiking neural network. Several techniques, including event-driven architecture and a fully optimized iterative computation approach, are adopted to minimize the hardware utilization and power consumption for the hardware implementation of online learning. Experiment results show that the proposed design reaches the accuracy of 87.36% and 83% for the Mixed National Institute of Standards and Technology database (MNIST) and ECG classification. The hardware architecture is implemented on a Zynq-7020 FPGA. Implementation results show that the Look-Up Table (LUT) and Flip Flops (FF) utilization reduced by 14.87 and 7.34 times, respectively, and the power consumption reduced by 21.69% compared to state of the art.

High-precision multi-channel bio-signals are the basis of reliable and accurate wearable and implantable continuous health monitoring systems. However, the limitations of transmission bandwidth and computation resources of these systems pose heavy constraints on either the communication or direct processing of the large volume of physiological signals. Although signal compression can be adopted to compress the signals, most existing compression methods are computationally expensive and completely overlook the actual monitoring task purpose, which causes the discard of task-relevant information. Moreover, a complex reconstruction process is needed for further signal analysis at the cost of a heavy computational burden for downstream devices. We propose in this paper a novel flexible health monitoring framework where the signal is compressed with a low computation and hardware cost in-sensor compression matrix, trained in a task-aware fashion to preserve task-relevant information. The resulting compressed signals can be transmitted with significantly lower bandwidth, analyzed directly without a dedicated reconstruction process, or reconstructed with high fidelity. We demonstrate the effectiveness of our proposed framework by showcasing a seizure monitoring system. Prediction accuracy, sensitivity, false prediction rate, and signal reconstruction quality are reported under different compression ratios. Extensive experiments show that the proposed framework is accurate, with an average seizure prediction accuracy of 91.44%.

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610$\mu \text{W}$and$850~\mu \text{W}$across the measured deadtime ranges while$\text{C}_{\mathrm {L}} =12$pF,$\text{V}_{\mathrm {dd}} =3.3$V, and$\text{f}_{\mathrm {s}}=200$kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of$150\mu $m$\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum$\text{T}_{\mathrm {DLH}}$and optimal$\text{T}_{\mathrm {DHL}}$at$\text{I}_{\mathrm {Load}} =25$mA is improved by 12% compared to a converter with a fixed deadtime of$\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ns.

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35$\mu \text{m}$technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of$70\,\,\mu \text{m}\,\,\times 180\,\,\mu \text{m}$. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

A CMOS Hall-based fully integrated isolation amplifier for differential voltage sensing is presented in this work. The design is fabricated in a$0.35 \mu \text{m}$CMOS process in which the high voltage (HV) side of the amplifier contains a coil driver while the low voltage (LV) side includes a Hall-effect sensor, low-noise amplifier, programmable-gain amplifier, filter, and chopper switches. Another Hall sensor performs the digital isolation using the on-off keying (OOK) technique for clock recovery. The introduced prototype achieves above 120 dB of isolation mode rejection (IMR) at 60 Hz and operates at a continuous isolation working voltage of 0.6 kV. It has also a maximum nonlinearity of 0.64 %, an input-referred offset of 1 mV, a 40 dB full-scale signal-to-noise ratio over a 40 kHz bandwidth, and a spurious-free dynamic range of 64 dB. The silicon area for each of the two separate dices employed for the HV and LV side of the isolation amplifier is 1 mm2with a power consumption of 7.6 mW and 9.9 mW respectively. The achieved miniaturized size of the isolation components, as well as their significantly low-power consumption, ensure the suitability of the proposed isolation amplifier for multi-channel readout circuit applications.

Radio frequency energy harvesting (RFEH) is very attractive for the Internet of things (IoT) and self-powered micro-systems such as wearable biomedical devices and wireless sensor networks. This paper proposes, analyzes, and implements a new RF-DC converter in standard 130 nm CMOS technology. The developed converter is designed and optimized for ultra-low-power IoT and wearable biomedical applications using the 900 MHz ISM band. The proposed 10-stage cross-connected rectifier compensates the transistors threshold voltage by using both dynamic and static bias compensation techniques. An analytical model of the rectifier based on the MOSFET transistor equations is presented, allowing optimization of the rectifier as a function of the number of stages and transistors sizing, improving the sensitivity and the input power range of the converter. The measurement results demonstrate a sensitivity of −25.5 dBm for 1 V output across a 5-$\text{M}\Omega $resistive load and −29 dBm for a 100$\text{M}\Omega $load, which is better than the best previously reported results. The measured peak end-to-end efficiency of the proposed harvester is 42.4% at −16 dBm input power, delivering 2.19 V to a 450$\text{k}\Omega $load.

Visual prostheses with both comprehensive visual signal processing capability and energy efficiency are becoming increasingly demanded in the age of intelligent personal healthcare, particularly with the rise of wearable and implantable devices. To address this trend, we propose NeuroSEE, a neuromorphic energy-efficient processing framework that combines a spike representation encoding technique and a bio-inspired processing method. This framework first utilizes sparse spike trains to represent visual information, and then a bio-inspired spiking neural network (SNN) is adopted to process the spike trains. The SNN model makes use of an IF neuron with multiple spike-firing rates to decrease the energy consumption without compensating for prediction performance. The experimental results indicate that when predicting the response of the primary visual cortex, the framework achieves a state-of-the-art Pearson correlation coefficient performance. Spike-based recording and processing methods simplify the storage and transmission of redundant scene information and complex calculation processes. It could reduce power consumption by 15 times compared with the existing Convolutional neural network (CNN) processing framework. The proposed NeuroSEE framework predicts the response of the primary visual cortex in an energy efficient manner, making it a powerful tool for visual prostheses.

This paper presents the design and analysis of combining input-voltage feedforward and proportional-integral (PI) controllers to regulate the output voltage of DC-DC Buck converter subject to input line disturbances. Non-idealities of the Buck converter such as passive and active components parasitics are included in the mathematical model obtained by the statespace averaging (SSA) technique for accurate control. The stability boundary locus approach is used to graphically analyze the system stability. It guides the design of the PI controller gains and the feedforward scaling factor to achieve desired phase and gain margins. Analysis shows that the feedforward scaling factor affects the stability regions of the closed-loop system and can limit the possible PI controller gains for certain phase and gain margins; 75oand 9.54 dB in our case. The results are verified by a Simulink model developed for the Buck converter system.

A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35μm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diode- supercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 μmx100 μm.

Several high specificity and sensitivity seizure prediction methods with convolutional neural networks (CNNs) are reported. However, CNNs are computationally expensive and power hungry. These inconveniences make CNN-based methods hard to be implemented on wearable devices. Motivated by the energy-efficient spiking neural networks (SNNs), a neuromorphic computing approach for seizure prediction is proposed in this work. This approach uses a designed gaussian random discrete encoder to generate spike sequences from the EEG samples and make predictions in a spiking convolutional neural network (Spiking-CNN) which combines the advantages of CNNs and SNNs. The experimental results show that the sensitivity, specificity and AUC can remain 95.1%, 99.2% and 0.912 respectively while the computation complexity is reduced by 98.58% compared to CNN, indicating that the proposed Spiking-CNN is hardware friendly and of high precision.

This multidisciplinary panel of experts in medicine considers the applications and impacts of technological innovations like Artificial Intelligence, automation, and the Internet of Things, focusing especially on addressing global health challenges, particularly for the post-COVID-19 pandemic era, including in developing nations and underserved populations. Panelists will discuss the opportunities and challenges of telemedicine, cybercare, homecare, treating noncommunicable diseases and preventing communicable diseases, as well as the development of reliable policy and standards for privacy and security of digital innovations.

Power consumption is an important limitation in designing analog-to-digital converters (ADCs) used in low-power sensing applications. This paper estimates analytically the power bound of a two-step multi-stage noise-shaping successive-approximation-register incremental ADC (two-step MASH NS-SAR IADC) proposed in our previous work. Our model considers the impacts of thermal noise, mismatch, and CMOS process (minimum feature size in CMOS technologies) on the power bounds of the proposed IADC. The analytic results show that thermal noise and CMOS process requirements determine the power consumption lower bounds in high and low resolutions, respectively. A comparison with the most competitive single-loop delta-sigma (ΔΣ) IADC shows a 3-dB higher theoretical figure-of-merit (FoM) for our proposed IADC when the resolutions are higher than 12-bit. Our proposed systematic analysis can be used to estimate the power bounds of amplifier-based NS-SAR ADCs used in either ΔΣ or incremental mode with multi-stage and multi-step topologies designed in various CMOS technologies. The reported analytic results are confirmed by experimental results of previously reported implementations.

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V.

A multi-stage noise shaping (MASH) analog to digital converter (ADC) architecture is presented in this paper. This architecture combines the features of noise shaping SAR (NS-SAR) with the MASH scheme to achieve a higher order noise shaping. This ADC does not suffer from the complexity issue of conventional MASH delta sigma (ΔΣ) structures, and it does not require operational transconductance amplifier-based analog integrators. It also exhibits a high resolution and moderate bandwidth while using a low oversampling ratio (OSR). These merits make the introduced architecture suitable for large number of applications, such as internet of things (IoT) and biomedical devices. The paper proposes MATLAB behavioral models along with macro models used to simulate the presented architecture to show the efficiency of the proposed ADC featuring a signal-to-quantization-noise ratio (SQNR) of 105 dB for an OSR of 10 at a sampling frequency of 10 MHz.

In this paper, a wide range, area efficient, and high-precision pulse generator is presented. The proposed architecture exploits a CMOS thyristor delay element, and benefits from its decent advantages. The proposed circuit generates an input-independent, stable, and accurate pulse width signal. The pulse-width can be tuned continuously in the range of 1.5 ns to 45 ms. This novel structure is a part of a control circuit intended for recognizing the eventual faults and errors in industrial sensor interfaces. The presented circuits have been implemented in 0.35 μm standard CMOS process. It consumes 0.11 to 7.42 mW power from a 3.3 V supply. The total occupied area is about 0.018 mm2and the maximum operation frequency of the proposed pulse generator is 331 MHz.

Equilibrium Propagation (EP) is a novel biologically plausible algorithm for training deep neural networks. However, discrete time implementations of EP could not exploit the full potential of its proposed framework, because the relaxation step is slow on digital architectures. Here, we propose an analog circuit implementation for the relaxation process to accelerate its convergence. In this implementation, the optimization process is executed based on the continuous-time dynamics of EP. Our circuit is validated using a Continuous Hopfield Network prototype emulating the XOR function. This implementation improved the convergence time of EP by a factor of 250 compared to its Python counterpart. As this implementation is scalable to learn more complex functions, it has the potential to be applied on higher-dimensionality datasets.

A novel non-overlapping signal generator intended for power-converters operation is presented. This switched capacitor circuit architecture-based sensor and actuator interface is implemented in AMS-H35B4D3 technology and consumes a power of 51.8 mW from a 3.3V-supply at 1 Mbps. Two-sided wide swing current source, two capacitors, Schmitt triggers and three transmission gates are employed on each side of the current source for implementing this versatile building block. The circuit provides needed dead-time to the power amplifier for high and low voltage applications. The time period of the master CLK is 1μs. The proposed circuit successfully generates two outputs with 0.4813 μs (~half of period) non-overlapping delay between the phases. It occupies an area of 70 μm×180 μm from the total half bridge area of 800 μm×1370 μm.

This paper presents a front-end amplifier with a novel isolation technique. The proposed isolation technique employs a single on chip stacked spiral coils to generate a signal dependent magnetic field. Also, an integrated Hall effect sensor implemented under the coil detects the generated magnetic field, while achieving a minimum isolation working voltage of 430 V. In this configuration, no signal modulation is required and frequencies from DC to 50 kHz are transmitted over the isolation barrier. On the high voltage side, a single bit programmable gain instrumentation amplifier increases the 3-dB frequency of the common mode rejection ratio and supports input differential voltage ranging from -2.5 to 2.5 V. Also, on the low voltage side, a dB-linear PGA with 6 bits of gain setting adapt the signal to the input dynamic range of an ADC. Finally, a programmable second order Butterworth Anti-Aliasing Filter conditioned the signal before conversion.

Nowadays, several deep learning methods are proposed to tackle the challenge of epileptic seizure prediction. However, these methods still cannot be implemented as part of implantable or efficient wearable devices due to their large hardware and corresponding high-power consumption. They usually require complex feature extraction process, large memory for storing high precision parameters and complex arithmetic computation, which greatly increases required hardware resources. Moreover, available yield poor prediction performance, because they adopt network architecture directly from image recognition applications fails to accurately consider the characteristics of EEG signals. We propose in this paper a hardware-friendly network called Binary Single-dimensional Convolutional Neural Network (BSDCNN) intended for epileptic seizure prediction. BSDCNN utilizes 1D convolutional kernels to improve prediction performance. All parameters are binarized to reduce the required computation and storage, except the first layer. Overall area under curve, sensitivity, and false prediction rate reaches 0.915, 89.26%, 0.117/h and 0.970, 94.69%, 0.095/h on American Epilepsy Society Seizure Prediction Challenge (AES) dataset and the CHB-MIT one respectively. The proposed architecture outperforms recent works while offering 7.2 and 25.5 times reductions on the size of parameter and computation, respectively.

A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, utilizing a per-bit silicon area of less than 350 μm2. Although such very small area allows for embedding in dense configurable fabrics (field-programmable gate arrays) and wafer-scale integration, the overall performance is not sacrificed as reported measurements show a signal-tonoise ratio of 51.87 dB and a spurious-free dynamic range of 42.31 dB, at 10 MS/s providing 7.6 effective bits. Moreover, the proposed architecture benefits from dynamic calibration capabilities, as any converter output can be finely adjusted over a range of 25 mV. This proposed DAC is also extensively reused in the same defect-tolerant network for a successive approximation register-analog-to-digital converter, as well as for a configurable voltage reference.

We propose in this paper a high-temperature non-linear modeling for the I-V characteristics of GaN150 HEMT. Three different data-driven models were developed for a temperature range varying from 25°C to 250°C, by using three machine learning regression techniques namely: The Artificial Neural Network (ANN), the Support Vector Machine (SVM) and the Decision Tree (DT). Experiments were conducted on a GaN150 device with a width of 40 μm and accordingly, a set of measurements were obtained and exploited to build the device model. The three models were evaluated based on their ability to predict the I-V characteristics outside the temperature range (greater than 250°C) and their mean square error. The obtained results show that the models predict the device characteristics correctly based on the calculated mean squared error between the actual and predicted characteristics.

We describe in this paper a model for the I-V characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) working in high-temperature environments up to 250°C. Modeling of this emerging technology is a very significant step toward incorporating the technology in harsh environment applications. An extended version of the Angelov model is modified in this paper to consider the temperature as a variable. The developed model is fitted to the experimental I-V data using MATLAB. The reported experimental data are in good agreement with the model outputs over the specified temperature range. Moreover, the model was validated using the Spectre circuit simulator.

A gated ring oscillator (GRO) based multi-stage noise-shaping ΔΣ modulator (ΔΣM) is presented in this paper. Loop-filter integrators followed by a digitally implemented GRO make the proposed architecture suitable for scaling-friendly implementations. Quantization noise of the first stage is represented in the time domain and it eases the quantization error extraction with a simple digital circuitry. The GRO offers inherent dynamic element matching, and hence no extra circuitry is needed to linearize the DACs in the feedback path. Time-domain behavioral simulations are shown to study of main GRO non-idealities considering a discrete-time MASH 3-1 topology, featuring a SNDR of 94 dB for an OSR of 16 over a 2-MHz signal bandwidth.

Optical neural stimulation using optogenetic technique plays an important role in neuroscience applications and neuroprosthetic solutions. Most optogenetic applications require power efficient photostimulation tools that can provide sufficient optic power for stimulation of photosensitized neural cells with desired spatial and temporal resolutions. In this paper, we propose an active control of custom-assembled μLED arrays for optogenetic photostimulation tools. The designed circuit provides required forward voltage (3.3V) and current (20mA) to the corresponding μLEDs without sacrificing optic power or temporal resolution. The active control system has been realized using AMS 0.35 μm CMOS process and the performance of the design has been verified through post-layout simulation. The proposed design can operate under different forward voltages and hence, can be adopted for driving several types of μLEDs.

This paper presents a novel ultra-low power rectifier for RF energy harvester, designed and implemented in standard 130 nm CMOS technology. The proposed 915 MHz ISM band RF energy harvester is designed for wearable medical devices and internet of things (IoT) applications. An off-chip differential matching network passively boosts the low-level incoming AC signal generated by the antenna. Then, a novel self-compensated cross-coupled rectifier is designed to convert the AC signal into a DC output voltage. The rectifier is comprised of 10 stages and it uses both dynamic and static bias compensation to decrease the transistors forward voltage drop. The post-layout simulation results demonstrate a sensitivity of -30.5 dBm for 1 V output at a capacitive load which is lower than the current state-of-the-art. The peak end-to-end efficiency is 42.8 % at -16 dBm input power, delivering 2.32 V at 0.5 MΩ resistor load.

A small-size, battery-less optical ID transmission node operated by optical energy harvesting will be demonstrated. The device is shown in Figs. 1 and. The device is as small as 12 mm in diameter, and it can be operated with a handy IR flashlight (see Fig. 3). Only a desk is needed to put some devices and flashlights on. On the desk, a laptop PC will be placed to provide additional information.

In this paper, we present a compact and low power bandpass amplifier in the frequency range between 1.5 Hz and 21 kHz. It was designed and simulated in a 65-nm standard Complementary Metal-Oxide-Semiconductor process and 1 V power supply. Decreasing the low-cutoff frequency of amplifier to a few Hz in 65-nm technology with modest feedback capacitance is challenging. Thus, this low-cutoff frequency reduction has been performed in two stages: first, by decreasing the OTA's transconductance and second, by using cross-coupled positive feedback that decreased the low-cutoff frequency to around 1 Hz. At the end applying T network-based capacitive feedback in this amplifier decreased the whole capacitance and realized a compact amplifier. The results showed the gain of 30.4 dB for the amplifier and 0.6 μW dissipation from a 1 V power supply.

A fully integrated current sensing interface chip employing a capacitive-feedback transimpedance amplifier (TIA) is presented. A robust dc current removal block is proposed to prevent the dc portion of the input current from saturating the output voltage. This block allows the TIA to operate in the presence of a wide range of input dc currents, and the cancellation loop is designed to enhance its stability. The TIA is fully integrated in a standard 0.13 μm CMOS technology, and a gain of 170 dBΩ is achieved without requiring any off-chip resistors. The integrated input-referred current noise of the interface circuit is 0.4, 3.8, and 52 pARMS within 0.01, 0.1, and 1 MHz integration bandwidths, respectively.

This paper describes an implementation of low power frequency modulated ultra-wideband (FM-UWB) transmitter in standard 130nm CMOS technology. The transmitter is designed to operate in the range of 3.328-4.608 GHz. A relaxation oscillator is used to generate the subcarrier signal which is calibrated by a phase-locked loop (PLL). The RF carrier is generated using a voltage-controlled oscillator (VCO). A proposed calibration scheme based on a PLL is utilized to calibrate both the upper and the lower frequencies of the operation band. The proposed FM-UWB transmitter consumes 835μW from a 1.2V supply at 500kbps achieving an energy efficiency of 1.67nJ/bit.

This paper presents a new approach towards the development of a free-breathing micro-spirometer system on a single chip for point-of-care (POC) diagnosis of lung diseases. In this paper, we take the first step by designing and implementing a cantilever array chip using a standard micro-electromechanical system (MEMS) process. Each cantilever beam is incorporated with capacitive electrodes for sensing the cantilever deflection. Herein we also put forward a custom-made readout interface circuit for the measurement of minute capacitive changes and for data acquisition purposes. Furthermore, we demonstrate and discuss the fabrication and characterization and spirometry results. Based on these results, the device is used for measuring the breathing airflow with a resolution better than 12 bits. These preliminary results reveal the functionality and applicability of the propose d system for POC diagnostics applications related to lung disease.

The paper presents the concept, layout and simulation results for a combined chemical and optical 92×92 pixel array designed as a 3.18×3.18mm2ASIC in standard AMS 0.35μm CMOS technology. The optical pixels employ PN junctions as photodiodes, while the chemical pixels use ISFETs that are pH sensitive with the standard passivation layer of the process. Local light intensity and pH level are encoded using pulse frequency modulation (PFM) and conveyed off-chip using the address event representation (AER) protocol. The chip has been conceived specifically to characterize a light sensitive biomolecular thin film that is in turn intended as a retinal implant for the treatment of end-stage retinal degenerative diseases.

Modern sensor networks are evolving toward wireless interfaces for both power and data transmission. Design of these devices is challenging, especially when both power and data transmission must reach a harsh environment subject to high temperature, high pressure and through thick metallic layers. This paper reports the design and simulation of an inductive power transfer (IPT) system, which characterizes achievable link efficiency. The problem formulation comes from a family of aerospace applications in which electronic must operate at high temperature (500°C) and high pressure (100 bar) and in which a metal casing (15mm thick) isolates the harsh environment from the environment. Specifically, the requirements of booster rockets in aerospace industry are considered. The proposed IPT system was modeled and simulate d using COMSOL. Reported results demonstrate the feasibility of wirelessly transferring power to a high temperature and high pressure zone through various metallic layers using custom electromagnetic link configurations. Power transfer efficiencies of 38% and 15.5% are reported with Titanium and Steel metal booster interfaces at resonance frequencies of 450Hz and 220Hz respectively.

A 0.9 V feed forward, op-amp shared MASH structure delta sigma modulator for low power sensor interface applications in 0.18 μm CMOS process is presented in this paper. A modified feed forward op-amp shared structure is implemented to reduce the integrators output swings. Due to opamp sharing, the power hungry adder, which constitutes a first challenge in conventional feed forward structures when used in lower-power applications, is eliminated. Moreover, the signal transfer function is modified to be equal to unity in each stage, addressing the second challenge in the conventional feed forward architecture. To reduce the power consumption of the modulator, a fully-differential inverter-based operational transconductance amplifier (OTA) is adopted. Flicker noise is alleviated with the adoption of a chopper stabilization technique. The proposed modulator is sampled at 5.12 MHz for a bandwidth of 20 kHz (OSR of 128). Post-layout simulations show that the modulator achieves 91 dB/89 dB SNR/SNDR respectively while consuming only 65 μW of power.

Signal processing is an important component in advanced neural recording devices, which facilitates increasing number of neuroscientific investigations. Recently, template matching and compressed sensing (CS) techniques have attracted attention for their use in spike detection and data compression respectively. In this article, we propose an online adaptive digital spike detection and data compression system using Bayesian inference-based template matching and the CS technique. Bayesian inference is applied for spike detection using either pre-generated or automatically generated templates. The proposed module locates the spikes with a high-detection accuracy. Additionally, it integrates the CS technique and applies a sensing matrix, called a Minimum Euclidean or Manhattan Distance Cluster-based (MDC) matrix, to compress signals. Using the MDC matrix, the proposed system cannot only compress a signal with a high-compression rate (CR) but also with a low reconstruction error (RER).

In this Paper, we propose a new method for safe electrical neural stimulation. Current mode digital-to-analog converters are used to generate the cathodic and the anodic stimulation phases. A sample-and-hold and a window comparator circuit are used to compare the voltage of the electrode and the tissue with a target value within a safe voltage range of -50 mV to +50 mV. When the electrode voltage falls below the lower bound or above the upper bound of such a safe voltage range, the anodic stimulation pulse width is modified in such a way that the electrode voltage remains in the safe range. High-level pulse shrinking (HLPS) and low-level pulse shrinking (HLPS) elements are used in digital part to modify anodic pulse width. Simulation results for the proposed circuit implemented in a 0.18μm 1P6M CMOS technology confirm proper functioning and show that the proposed circuit requires extremely low power compared to other charge balancing schemes, with a power consumption of 4.2 μW.

In this paper we present a compact, low-cost and re-usable cell-based biosensor that can be employed as a versatile tool for cell detection and monitoring. The proposed biosensor consists of an array of 8×8 capacitive sensors working based on the fully differential charge-based measurement technique. The analog output voltage coming from readout interface is converted to bit-streams using a DC-input ΣΔ modulator. The bit-streams are then acquired by a data acquisition system for further processing and display. We validate the chip functionality using various organic solvents with different dielectric constants. Moreover, we show the response of the chip to different concentrations of Polytyrene beads that have the same electrical properties as the living cells. The experimental results show that the chip allows the detection of a wide range of Polystyrene beads concentrations from as low as 10 beads/ml to 100k beads/ml. Due to its compactness, fast response and low complexity, the device can be used as an efficient alternative to traditionally labor-intensive cell analyses processes and it can be advantageous in different fields of biology and medicine.

This work concerns a compact, low-cost and reusable cell-based biosensor which can be employed as a versatile tool to transit Petri dish based experiments from the traditionally labor-intensive process to an automated and streamlined process which is significantly advantageous in different fields of biology and medicine. We demonstrate a fully integrated CMOS capacitive biosensor for tracking the growth of adherent cells and analyzing the effect of anti-cancer agents on the cells behavior. The proposed cell-based platform is composed of an array of 8×8 capacitive sensors working based on the fully differential charge-based measurement technique. The analog output voltage coming from readout interface is converted to a digital bit stream using on-chip DC-input ΣΔ modulator. A novel reconfigurable clocking scheme is proposed which allows reaching to a very high sensitivity and capacitance detection range.

In this paper, we present a multi-parameter CMOS biosensor for simultaneous measuring of extracellular acidification and cell growth rate. The proposed device, fabricated in TSMC 0.35 μm technology, consists of an array of ISFET-based pH sensors and capacitive sensors integrated in one single chip. The capacitive sensors are realized by a fully differential capacitance to voltage converter, a differential ΣΔ modulator, and interdigitated electrodes built on top-most metal layer (M4) in 0.35 μm CMOS process. The pH sensor is composed of an array of 8×8 inverters employing a pair of p-type and n-type ISFETs sharing the same ion sensitive membrane. The complementary pair of ISFETs works as a chemical switch that can be used for pH thresholding and is functional in the wide pH range of 1 to 14 with the sensitivity of 50 mV/pH. We show the functionality of proposed hybrid biosensor by exposing the device to various organic solvents with different dielectric constants as well as different pH buffers. Thereafter we discuss the functionality and applicability of the proposed device for life science applications by demonstrating the response of the chip to Human Lung Carcinoma (H1299) cell line.

In Optical Time-Resolved Reflectance, a pair of injecting and collecting optical fibers are placed at a fixed source-detector separation from each other typically in the range of 20 to 40mm limited by the detector dynamic range. To increase the sensitivity to higher penetration depth of investigation, the source and the detector separation should be small. We first show with simulation results that short source-detector separations results in the detection of a higher number of photons coming from a greater depth. However, at these shorter distances the number of early arriving photons also increase (mainly coming from the skull and scalp regions in brain imaging) which is a constraint. To reject the early arriving photons we need a gated detector to enable detections at specified time windows. We then confirm these results in an experimental study using a simplified photon detection scheme. The dependency of the photon counts on the gate window and the source-detector separation is analyzed. We conclude that placing the laser source and the detector quite close to each other is an option to consider for the design of optodes so as to improve the image quality in various biomedical appications.

As the world's population ages, healthcare costs become heavy burdens worldwide. Portable point-of-care diagnostic devices, such as glucose meters, can significantly reduce the costs associated with patient care. There are many of small biological molecules present in biological samples which are of interest in healthcare applications. In this paper, a simple low-cost impedance detection circuit has been designed to detect different biomolecules such as DNA, proteins and other metabolites. In particular, the impedance across an electrode will change due to the binding of target biomolecules and gold nanoparticles. Experimental results show that the device can measure impedance changes with accuracy in the range of ±3%.

We present an integrated biosensor platform using ion-sensitive field effect transistor (ISFET) device for monitoring pH levels in cell culture medium. Each pixel in the 8×8 array employs a pair of p-type and n-type ISFETs sharing the same ion sensitive membrane. The complementary pair of ISFETs works as a chemical switch that can be used for pH thresholding. The proposed biosensor is fabricated using TSMC 0.35 μm standard CMOS technology. We show the functionality and sensitivity of device by using buffer solutions with different pH values. The proposed biosensor is functional in the wide pH range of 1 to 14 with the sensitivity of 50 mV/pH. Due to its low complexity, pH sensitivity, and biocompatibility, this platform can be used for cellular studies applications such as cancer cell growth monitoring.

This paper reports an energy-efficient waveform generator, dedicated to implantable retinal microstimulators. The circuit features flexible current-mode stimuli such as rising and falling exponential pulses in addition to rectangular pulses. In order to apply the stimulation current to the electrode at the defined current levels (±96μA) and with sufficient voltage headroom (±3V), a class AB second generation current conveyor is designed as the output stage. To upconvert the 1.2-V supply voltage to ±3.3V, the output stage is equipped with an on-chip electrode-tissue driver. Duration of the generated current pulses is programmable within the range of 100μs to 3ms. Current-steering DACs are used to set the amplitudes of pulses. They exhibit DNL and INL of 0.04 and 0.17LSB, respectively. The amplitude, duration, and time constant of exponential pulses are independently programmable. Designed in the IBM in 130nm process, the circuit consumes 1.5×1.5 mm2of silicon area. Post-layout simulation results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance as high as 30kΩ. The proposed design consumes a maximum of 1.2mW in the rectangular pulse mode.

This paper concerns a custom digital signal processor (CDSP) dedicated to evaluate a sensory feedback from a neuroprosthetic implant that is intended to restore the storage and voiding functions of the urinary bladder. The proposed CDSP executes the neural source identification through an on-the-fly spike-sorting process followed by neural decoding of the bladder volume. In addition to in situ measurement of the urine volume, its wireless transmission to a base station, and informing user about the bladder status, this sensory information is intended for a closed-loop electrical stimulation interface dedicated to tune up the stimulation parameters to ensure continence and bladder voiding. To assess feasibility, the CDSP prototype was deployed in a low-power FPGA (Actel Igloo). The results of the tests performed using synthetic realistic signals and real signals recorded from rats' bladder during acute experiments, show the feasibility of the proposed device.

In this paper, we present a new dielectrophoretic microfluidic technique in a modular Lab-on-Chip (LoC) platform. The proposed LoC has a reconfigurable topology. It generates a wide range of signals depending on the analyzed liquid with a variable frequency up to 1.2 MHz. In addition, a programmable phase shift circuit with a minimum phase step of 3.6° for each signal is implemented. The amplitude of each signal can be adjusted independently, and the latter can be distributed through 64 bidirectional electrodes. Each electrode can be enabled or disabled individually. Moreover, device includes capacitive sensing stage for the measurement of the in-channel capacitance change induced by algae. Furthermore, The architecture of the proposed system is versatile and can be adjusted to different cell manipulation applications. The presented LoC was tested with 15 μm algae cells.

We present a new Charge Based Capacitance Measurement (CBCM) CMOS sensor for Lab-on-Chip applications. This integrated capacitive sensor consists of a fully differential capacitance to voltage converter, a sigma delta (ΣΔ) modulator, and interdigitated electrodes realized on top metal layer in 0.35 µm CMOS process. The proposed CMOS capacitive sensor offers higher dynamic-range (10 fF) and sensitivity (350 mV/fF) in comparison to our previously reported core-CBCM capacitive sensors. We proved this significant improvement by demonstrating the chemical solvent concentration measurements and discussing the potential applications in environmental monitoring and water safety applications.

This work focuses on the circuit and system implementation of a magnetic immunoassay based microsystem platform to be used as sensor terminal for detecting protein toxins in environment. Three main challenges facing this work-the design of a high performance sensor, the packaging technique and the design of integrated circuit are introduced. Planar microcoil array fabricated both on silicon substrate and polymer substrate are exploited as sensor of magnetic particles, whereas microchannel and ultra thin bottom microplate for traditional ELISA was used for reagents, correspondingly. Simulation results of two detection circuits prove that our system is able to detect magnetic particles in different volumes, thus the proposed microsystem has potential for medical diagnostics, food pathogen detection or water analysis.

Microstimulation is a feasible method targeting visual impairment. In this paper, the authors focus on intra‐cortical stimulation to cover the broader spectrum of the issue with the aim of providing a better suited visual aid. They present an overall modular architecture and focus on creating re‐usable image processing tools that can be used for image simplification and recognition tasks. One of the main challenges in the image processing path is the real‐time restriction; hence they resort to field‐programmable gate array (FPGA) hardware acceleration. Herein they demonstrate and describe the architecture of an image feature extractor based on the difference of Gaussians that is at once accurate, generic and low on resources. This architecture also features a Huffman encoding engine that proves useful when resorting to software–hardware (SW–HW) hybrid implementations, and a technique of calibrating and calculating the phosphene map.

We present in this paper a new architecture of a visual intracortical microstimulator, which is composed of an external controller providing electromagnetic energy and capacitive-link based high data rate link, and a multi-unit energy-efficient implant. The latter is composed of 2 full custom chips. The first one is a multiwaveform stimuli generator dedicated to supply microstimulation-based constant current to the second chip grouping a multichannel high-impedance microelectrode driver (MED). The stimuli generator is featured with several new power-efficient building blocks such as high-performance current mirrors, low-area source/sink current-mode digital-to-analog converters (DACs), and low-power dedicated controller. The highly-configurable MED, which provides the multi-level current (2 to 196 μA), drives an array of microelectrodes through high-voltage switches. The stimuli generator is implemented in 1.2/3.3 V IBM CMOS 0.13 μm technology. However the output MED is fabricated in DALSA 0.8 μm 5V/20V CMOS/DMOS technology. The latter supplies needed compliance voltage of 10V across high impedance (average value of 100kΩ) microelectrode-tissue interface. The silicon areas of the low-voltage and highvoltage chips are 1.75×1.75 mm2and 4.0×4.0 mm2respectively. Post-layout simulation results are provided to show the expected operation of the device.

In this work we propose a mismatch-robust VCO frequency comparison circuit based on the absolute period-measurement of the two frequencies. The main idea of the work is to increase the overall calibration precision by employing a multiplexer in the input, thereby allowing both signals to use the same path including a single Time-to-Voltage Converter circuit (TVC). Ultimately, this would result in lower overall mismatch and better accuracy compared to the case where the current sources of the two different TVCs must be carefully matched. The simulated frequency error is found to be less than 0.8% after only 4 reference cycles. The proposed scheme is also simulated against Process, Voltage, and Temperature (PVT) variations.

We propose in this paper a portable lab-on-chip (LoC) platform dedicated for magnetic beads density measuring. The device consists of two main parts: disposable microfluidic structure and reusable electronic part. With results displayed on build-in LCD screen, the conventional bulky observation equipment is avoided. The principle of detection is that the presence of magnetic beads can affect the effective inductance of planar microcoil integrated inside of the LoC platform. In order to read out the inductance variation, we proposed a CMOS 0.18um application specific integrated circuit, which includes two different sensing blocks, namely impedance sensing and frequency sensing circuit. Preliminary experimental results with magnetic beads show that our proposed LoC platform allows measuring the density of magnetic beads in a wide range with fine linearity, either in continuous-flow microfluidics or digital mcirofluidics.

We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology.

In this paper, we design, evaluate and compare two phase-based passive stereovision architectures. We present two approaches to implement phase-based correspondence search algorithms in real-time for sparse stereovision applications. The first approach enhances the accuracy of the 1D phase correlation method. The second approach optimizes the 2D phase correlation method at the cost of degradation in disparity estimation accuracy. We report experimental results that encourage the use of the proposed systems in a 3D imaging device dedicated to cover vision for blinds through cortical visual stimulation. FPGA implementation running at 200 fps is described.

Two low-power high-voltage charge pumps have been designed to generate required voltage needed for intracortical microstimulation. High-voltage technology (0.8μm CMOS) has been used to generate high-supply voltage level with low-power consumption and low-voltage technology (0.13μm CMOS) has been used to investigate the possibility of generating high-supply voltage level overcoming the technology limitations. Both designs generate supply voltages more than 20V (>; ±10V) and consume low static power. The design in 0.8μm technology generates 24.52V supply voltage for no load and consumes 3.73mW static power. On the other hand, the design in 0.13μm CMOS technology generates 18.96 V for no load and consumes 0.8976mW static power.

In this paper, we describe the impact of square and non-square implementations of Current Source Arrays (CSAs) on the integral non-linearity (INL) of the thermometer-decoded current steering Digital to Analog Converters (DACs). The characteristics of several well-known switching sequences have been modeled and simulated using MATLAB in presence of different gradient error profiles. The simulation results show a significant correlation between the efficiency and performance of the employed switching strategy and the physical dimensions of the CSA. Based on the analysis of the obtained results, a strategy is introduced which includes a recursive approach towards the achievement of an optimum switching sequence for distributed current source-based DAC topologies.

Wake-up receivers (WuRx) have been recently employed in ultra-low power transceivers as a power efficient approach. In this work, we combine the idea of subsampling and the uncertain-IF structure in order to design and implement an ultralow-power WuRx for 915MHz ISM band applications. Based on extracted post-layout simulation results, the proposed WuRx draws 56μA from a 0.5-V supply and has a sensitivity of -70dBm. The new WuRx occupies an area of 0.15 mm2(including the pads) in TSMC90nm CMOS technology.

In this paper, we present system design of remote data recording for epileptic and stroke patients. We report wireless recording system combining near infra-red spectrometry (NIRS) in a comprehensive non-invasive evaluation and both electroencephalographic (EEG), and intracerebral EEG (icEEG) recording in presurgical evaluation. A Bluetooth and dual radio links were introduced for these recording. The Bluetooth-based device was embedded in a non-invasive multichannel EEG-NIRS system for easy portability and long term monitoring. On the other hand, the recorded icEEG signals from up to 128 channels through intracerebral electrodes are transmitted wirelessly to a remote base station. This transmitter front-end contains preamplifier, proper filtering, data converter and power amplifier. The RF back-end is based on commercial transceiver operated in the Medical Implant Communication Service (MICS) 400 MHz band. Power consumption of the front-end and transmitter are 0.75mW and 15mW, respectively. The proposed remote monitoring systems are validated in vitro using data recording from human patients.

In this article, we present an implantable closed-loop epilepsy prosthesis, which is dedicated to automatically detect seizure onsets based on intracerebral electroencephalographic (icEEG) recordings from intracranial electrode contacts and provide an electrical stimulation feedback to the same contacts in order to disrupt these seizures. A novel epileptic seizure detector and a dedicated electrical stimulator were assembled together with common recording electrodes to complete the proposed prosthesis. The seizure detector was implemented in CMOS 0.18- μ m by incorporating a new seizure detection algorithm that models time-amplitude and -frequency relationship in icEEG. The detector was validated offline on ten patients with refractory epilepsy and showed excellent performance for early detection of seizures. The electrical stimulator, used for suppressing the developing seizure, is composed of two biphasic channels and was assembled with embedded FPGA in a miniature PCB. The stimulator efficiency was evaluated on cadaveric animal brain tissue in an in vitro morphologic electrical model. Spatial characteristics of the voltage distribution in cortex were assessed in an attempt to identify optimal stimulation parameters required to affect the suspected epileptic focus. The experimental results suggest that lower frequency stimulation parameters cause significant amount of shunting of current through the cerebrospinal fluid; however higher frequency stimulation parameters produce effective spatial voltage distribution with lower stimulation charge.

This paper concerns the design of a Self-Strobed Delay Line Analog-to-Digital Converter (SSDL ADC) which is dedicated to digitally controlled Switched Mode Power Supply (SMPS) in implantable devices. The proposed windowed-based ADC can be adapted for different input signal levels. A new single slow delay cell is used to reduce power consumption, silicon area and hardware complexity. In implantable devices, further to low-power consumption and small area, the ADC is required to operate in continuously decreasing power supply. Consequently, a new current sink circuit is utilized to eleminate the need to redesign its controller if the characteristics of the supply devices change. The ADC is designed in AMS 0.35 μm CMOS process and it c an operate at high switching frequency. Spectre simulations of this ADC show a current consumption as low as 10μA/MHz, and the circuit can provide a wide operating range from zero to 1.5 V with quantization steps smaller than 1% of Vref.

We present in this paper a new CMOS interface for cell manipulation by dielectrophoresis and capacitive sensing system dedicated for a lab-on-a-chip. It fully integrates a signal generation circuit and a post-processing system to control parameters of each signal such as frequency, phase and amplitude. In addition, a large capacitive and low resistive load driver circuit is designed to deliver a current of 9 mA for each 16 electrodes as the microfluidic architecture is divided into 4 blocs containing 16 electrodes each one. Thus, the proposed CMOS chip provides 4-channel signals with individually controllable phase and amplitude. In addition, a capacitive sensing system has been integrated into the same chip to detect the capacitive change in the microchannel in the Lab-on-a-chip. The generated signals have a 2.5 peak-to-peak voltage range and 70 kHz frequency range while the detection system has a dynamic range of 1.5 V and a sensitivity of 11.8 fF/V.

In some magnetic beads based lab-on-chip (LoC) applications, such as purification and fast cell detection, high throughput capacity is required. In this paper, we propose an optimization method for the implementation of in-channel planar microcoils array. By generating more dispersed trapping centers and exploiting the array scanning scheme, the problem of interaction among magnetic beads is controlled and both power consumption and Joule heating are reduced. Simulation results by Finite Element Analysis software show that under the first order optimization, the proposed topology saves 69% power, while keeps approximate total trapping area, compared with the conventional topologies. The microfluidic structure combining the proposed coils array and operation scheme is suitable for high throughput LoC applications.

We describe in this paper an energy-efficient waveform generator which is dedicated to build a low-power intra-cortical implantable microstimulator. It features novel flexible current-mode stimuli such as half-sine and rising exponential pulses. The output stage of the proposed device consists of an electrode-tissue driver that generates high-voltage supplies on-chip in order to increase the voltage swing and maintain the stimulation in high-impedance interfaces which are due to small electrode areas. The current pulse duration may vary between 10 μs and 7 ms, while its amplitude varies from 2 to 200 μA. A current-mode digital to analog converter used to setup the current magnitude presents a DNL of 1.912×10-4LSB and an INL of 1.781×10-4LSB. The dynamic range of generated exponential current pulses reaches 40.66 dB with a linearity error <; ±0.5 dB. An output voltage swing of 14.5 V is reached allowing electrical stimulation through 150 kΩ microelectrode-tissue interfaces.

This paper proposes a fully integrated asynchronous step-down switched capacitor DC-DC conversion structure. The circuit uses a fully digital asynchronous state machine as the heart of the control circuitry. To minimize the switching losses, the asynchronous controller scales the switching frequency of the converter according to the load. It also turns on additional parallel switches when needed. This circuit regulates load voltages from 300 mV to 1.1 V derived from a 1.2 V input voltage. A total of 350 pF on chip capacitance was implemented to support a maximum of 250 μW load power, while providing efficiencies up to 80%. The circuit validating the proposed concepts was implemented in 0.13 μm CMOS technology.

This paper examines a new architecture that combines super regeneration and time-based signal processing concepts to implement frequency-to-time conversion. The proposed structure can also be used to perform LC-tank oscillators testing by using simple and low-resolution digital circuits. Its front-end consists of two cross-coupled oscillators, triggered in time by two step-like signals with a time separation that is externally controlled. The time separation, together with the cross coupling arrangement, results in a controlled start-up time of oscillation from which the frequency of oscillation can be deduced. The start-up time, extracted using envelope detection and coarse time digitization circuits, is then non-destructively measured. A proof-of-concept circuit is designed and laid out in a standard 90-nm CMOS process. Post-layout simulations confirm the feasibility of the proposed approach.

Currently emerging intracortical biosensing devices are promising alternative to allow studying the neural activity underlying cognitive functions and pathologies, understanding neurons interactions, locating onset seizures, detecting mind driven decisions, etc. This talk covers low-power analog circuits and packaging techniques used for the design and integration of biosensing Microsystems. Such devices are interconnected to intracortical neural tissues, and include high-reliability wireless links used to power up such implanted devices and bidirectionally exchange data with external base station. Global view of typical devices altogether with corresponding multidimensional challenges will be described. Special attention will be paid to report two case studies: 1) Automatic detection of action potentials from massively parallel channels, and 2) Epilepsy seizures monitoring and onset treatment.

The field of remote health monitoring now includes technologies such as home and mobile health monitoring, tele-retinal imaging, tele-radiology, remote cardiac monitoring, video conferencing and sensors for remote diagnosis and treatment to patients. In this regard, implantable wireless body sensor networks (IWBSNs) have recently emerged as an important and growing research area. These implantable sensors are required to be reliable, very small, battery-operated, and capable of collecting data, processing it, and transmitting it wirelessly and efficiently. Since these devices are required to run with limited resources (energy, processing, and memory), their utility protocols (collecting, processing, and communication) should be designed carefully, not only to work reliably but, more importantly, to be resource-efficient. The life time of the embedded batteries associated with these sensor nodes varies from a few days to a few weeks as was described in a previous work by the authors. In this paper, we propose a novel technique which allows the implanted sensor nodes to communicate with a base station located outside the body efficiently by consuming the minimum amount of energy. Our proposed protocol allows the battery to last significantly longer even for years with a gain of up to 100's times of power saving. This will improve the quality of patient life, and reduce risk of infection resulting from frequent chirurgical operations needed to replace such implantable batteries. Also, a new time synchronization algorithm is briefly introduced in this work that is especially applicable to our proposed communication protocol.

This tutorial covers circuits and systems techniques for the integration and packaging of implantable biosensing and neurostimulation devices. Such Microsystems, dedicated for interconnections to intracortical neural tissues, are wirelessly powered up while bidirectional data are exchanged between them and external controllers. Global view of main devices will be described, case studies related to massively parallel recording of neural signals will be shown, and special attention will be paid to monitoring and microstimulation in the primary visual cortex through an optimized number of electrode arrays and power management of these bioelectronic devices.

We present the design and implementation of linear-phase delay filters for ultra-low power neural signal processing. The filters are intended to implement a low-distortion delay element for automatic biopotential detection in neural recording implants. Continuous-time OTA-C filters are used to realize a 9th-order equiripple transfer function presenting a constant group delay. This analog delay allows to process neural waveforms with reduced overhead compared with digital delays. An allpass transfer function is used to implement such analog delay because it achieves wider constant-delay bandwidth than all-pole does. Two filters realizations are compared for implementing it: the cascaded structure and the inverse follow-the-leader feedback filter. Their respective strengths and drawbacks are assessed by modeling parasitics and non-idealities of OTAs, and using transistor-level simulations. A power budget of 200 nA is used in both filters. Experimental measurements with the chosen topology are presented and discussed.

Biomedical implants require wireless power and bidirectional data transfer. We propose a novel topology for a multiple carrier inductive link and compare two geometries for it. The orthogonal approach and the coplanar approach are these geometries. The principal challenge with multiple carriers is minimization of crosstalk, especially of power into data under lateral misalignment of the inner and outer coils. We show that a coplanar design allows keeping coupling of power into data under 15% with respect to the data coupling, even under lateral misalignments over 5 mm. In comparison, the orthogonal geometry reaches over 50% of parasitic coupling after a displacement of only 3 mm.

We present a low-power CMOS analog circuit for automatic detection of action potentials (APs) in extracellular recordings. The detector emphasizes neural APs by means of an energy-based preprocessor and locates them with a precision comparator. A linear-phase delay filter allows signal buffering to avoid truncated waveforms. The proposed detector isolates the identified waveforms in their entirety and completely preserves their features in order to improve shapes discrimination. The proposed circuit, implemented in a CMOS 0.18-mum process, achieves ultra low-power consumption as the whole detector dissipates only 781.5 nW. The detector has been validated in simulations with real neural signals and successfully detects APs from the underlying background activity.

A real-time, low-power digital quadrature demodulator is proposed to process ultrasound radio frequency signals in both pulse and continuous modes. Two finite impulse response filters are combined to build a Hilbert transform and a linear approximation architecture that allows achieving the required square root operations of quadrature demodulator. The complexity and accuracy of proposed demodulator are analyzed and successfully integrated in an FPGA as a low-power building block. Results show the proposed digital back-end demodulator is accurate, which motivates us to integrate in a miniaturized ultrasound receiver. Only 12 MULT18times18 and 1473 slices of the FPGA resources were required to synthesize the quadrature demodulator. Also, real-time images were acquired from a reference phantom demonstrating the feasibility of using the proposed architecture to accomplish real-time digital quadrature demodulation of echoes resulting from ultrasonic signals.

This paper concerns the design and implementation of a high data rate transmission system over a wireless inductive link. This system, dedicated to medical implantable devices, includes offset quadrature phase shift keying (OQPSK) modulator and demodulator. Both modulator modules feature a reduced complexity, low power, area efficient topologies and allow a high data rate transmission. The demodulator is an improved version from our previous QPSK design, which is based on a modified COSTAS loop. The post layout simulation of the implemented differential topology circuits using a 0.18μm CMOS technology achieves a data transmission rate of 8 Mbps with 13.56 MHz carrier frequency. The power consumptions of the implemented circuits are 16μW and 680μW for the modulator and demodulator respectively with a supply voltage of 1.8V.

This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is increased, and a protection from breakdown due to high voltages (HV) applied to its gate is achieved. Several HV circuits, including: positive voltage doubler and level-up shifter suitable for ultrasound sensing systems are built successfully around this technique. These circuits were implemented with the 0.8 μm CMOS/DMOS HV DALSA process. Experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 120V.

This paper presents the architecture of a stereoscopic-based range finder system. The proposed system is dedicated to a visual intracortical stimulator, which is intended to create artificial vision for people suffering from visual blindness. The 3D analysis of the environment is required allowing a better autonomy to the patient. The system consists of an emitter projecting light patterns from an infrared light source reflecting on a micro-mirrors matrix. Images from the illuminated scene are captured by a camera. The three-dimensional range is reconstructed from the distortions in the reflected and captured image. The approach consists of taking advantage of a high-speed camera and adapting the gray codification strategy to dynamic scenes. Tests have been made onto a moving plane surface leading to an error of 1.2 centimeters over a video sequence of two hundred range images.

In this paper, we present a charge-based interface circuit to detect minute capacitance changes for Laboratory-On-Chip applications. The interface circuits and sensing electrodes are implemented in 0.18 μm CMOS process. We describe the circuit design and then put forward simulation results. We also demonstrate and discuss the measurement results of fabricated capacitive sensor. These measurements reveal a high precision detection of sensing capacitance as less as 1 fF.

This paper concerns the design and implementation of a Bi-channel Selective Neurostimulator (BSN). It is dedicated to demonstrate the efficiency of bilateral sacral roots stimulation during chronic experiments in small animals (rats). The complete BSN implant has been highly miniaturized. It is powered and controlled by an inductive RF link and includes two channels. Even though they are meant for simultaneous operation, the channels outputs are synchronized to avoid drawing high stimulation currents at the same time. In addition, an alternating monophasic stimulation is used to reduce charge injection while keeping the advantage of charge balancing of the biphasic stimulation. The BSN prototype has been assembled on two circular printed circuit boards of 2-cm diameter each. With a total rms power consumption of less than 15mW, the BSN can provide a stimulation current up to 2mA, with maximum pulse width of 210μs and a maximum frequency of 2kHz.

Investigations on the electromagnetic behaviour of a low-power amplifier are led using the Extended-Integrated Circuit Emission Model (ICEM). This modeling approach is proposed on a mixed-signal (analog/digital) CMOS 0.18 μm circuit dedicated to neural signal recording. This ICEM allows coarse and fast studies of the electromagnetic compatibility of CMOS devices especially in characterizing the coupling phenomena that occurs at each building block inside the whole chip. ICEM simulations of power and ground bounces are more than 500 times faster than complete SPICE ones with a correct accuracy for first electromagnetic compatibility investigations. This quick modeling method allows for checking many different design or simulation configurations. For example, some simulation results show that substrate interactions and power/ground crosstalk increase the noise level of the low-noise amplifier, in particular in its low frequency domain.

A high data transfer rate quadrature phase shift keying (QPSK) demodulator is proposed for wireless implantable electronic medical devices. The QPSK demodulator is an improved version from our previous binary phase shift keying (BPSK) demodulator, which is based on a modified Costas loop. Simulated QPSK model under Matlab Simulink obtained a data transmission rate of 8 Mbps with 13.56 MHz carrier frequency. Also, implemented differential topology of the proposed circuit using a 0.18/spl mu/m CMOS technology achieves a data transmission rate up to 4Mbps with the same carrier frequency. The simulated power dissipation of the schematic is 0.75mW under 1.8V power supply.

We present the design and test of a portable wireless catheter system combining the simultaneous assessment of the transdiaphragmatic pressure and EMG of the diaphragm. The esophageal catheter includes two micro fabricated pressure sensors and five platinum ring electrodes. The low noise analog front-end features an electrode DC mismatch correction circuitry, a selectable gain (58 dB-97 dB) as well as a high CMRR (80.3 dB). Pressure signals are sampled at 1 kHz while EMG at 4 kHz. The data is transmitted over a wireless Bluetoothreg connection towards a computing host to display the received signals in real time. Testing of the device demonstrates its reliability to process pressure and EMG signals and to be used as a stand-alone respiratory parameters assessment device

Bandwidth of wireless multichannel neural recording systems is one of the most significant limitation to increase the number of channels monitored. Data compression is being efficiently used to process multichannel recordings. This paper explores discrete wavelet transform (DWT) processor architectures suited to compress ENGs and so, increase the number of channels. Low power consumption, low silicon area and specificity of multichannel neural recording systems are considered for this investigation. Six architectures were implemented and compared. All of them implement a 3 level Daubechies-4 wavelet decomposition. This comparative study allows to conclude that an excellent trade-off between power consumption and silicon area is obtained through a DWT polyphase structure using a careful balance of parallelism and folding. Also, it arises that multiplexing several channels toward a shared DWT processor provides the best savings for both, power and area

We present a bioamplifier suitable for massive integration in implantable recording medical devices. This amplifier achieves reduced size and lower power consumption, compared to previous designs, by means of a novel DC rejection scheme. DC rejection is achieved by an active integrator located in the feedback loop of the bioamplifier. It places a highpass cutoff frequency within the transfer function, which is set by a small capacitor and a MOS-Bipolar equivalent resistor. This configuration rejects large DC offset and drift that exist at the electrode-electrolyte interface without the need for input RC networks or area consuming capacitors feedback networks, thus preserving the bioamplifier's high input impedance and small size. The proposed bioamplifier, designed in a 0.18-mum CMOS process, provides a midband gain of 53 dB, passes the neural signal from 105 Hz to 9.2 kHz and achieves an input-referred noise of 5 muVrms. It occupies less than 0.064 mm2and dissipates 8.4muW

This paper presents a new analytical, empirical and behavioral modular model developed for accurate evaluation of power dissipation in power conversion chains (PCC) dedicated to power up an electronic implantable device. The model is suitable for power estimation/planning in early design stages, to determine the contribution of each circuit module on the total power consumption and to estimate the input and output voltages of these modules. It is based on average power consumption model and is coded in Verilog-A. The model is verified and the results were found to be in good agreement with state-of-the-art designs for bioelectronics devices. It is flexible and robust to changes in architecture and design parameters and provides accurate and valid results in a fraction of second for a large variety of parameter values. The ease of implementing desired modules and architectures makes the model more advantageous

A high-voltage operational amplifier (hvopamp) using dual-input floating-gate transistors for its feedback network is presented. The proposed hvopamp stabilizes the output DC voltage in the middle of its high-voltage power supply. Using floating-gate transistors eliminates the need for high-voltage resistor feedback networks. The integral nonlinearity (INL) of the hvopamp with floating gate feedback is 7% in the rail-to-rail output range, which is better than the performance of circuit using parasitic field-oxide MOS transistor as feedback network. The designer does not need to develop a new component, and can implement easily floating-gate transistors in most technologies, which facilitates design and improves the circuit robustness.

The design of a dual-source power scavenging and management system for ultra low power wireless medical applications is presented. Power scavenging is achieved by harvesting energy both from solar (primary) and RF power (secondary) sources. Depending on the available energy, the system can supply 1-2mW of power to a wireless device, with up to a 50% duty cycle. A radio-triggering based technique is used to control the activation and shutting down of the complete wireless system, and thus eliminates energy wasting wake-up periods. The system provides a regulated output voltage of 1.5V, with a total power consumption of less than 8.0/spl mu/W in the sleep mode, and 48/spl mu/W in the operating mode.

This paper describes a sub-sampling delta modulator operating at giga Hertz range to capture radio frequency signals. Down-conversion to low-IF is achieved by sub-sampling with a 1-bit quantizer. It presents higher bandwidth and SNR than those of the state-of-the-art sub-sampling modulators. Input carrier frequency can be followed over a wide range by controlling the sampling rate. Center frequency of the band-pass filters, which is placed at IF, is independent of input carrier frequency. A SNR higher than 55 dB is expected for a 2 MHz bandwidth signal modulated at 2-GHz frequency when the sampling rate is set to 990 mega samples per second

We present in this paper a current mediated active pixel sensor (APS) with variable image size and resolution for power saving, electronic zooming, and data reduction at the sensor level. The circuit can perform averaging of output signals in blocks of adjacent pixels (kernels) of size 1/spl times/1, 2/spl times/2 and 4/spl times/4, allowing data reduction without aliasing effects. To achieve this, a current approach is used, thus enabling high speed operation and low power supply capacity. A novel fixed pattern noise (FPN) reduction scheme using a compact circuitry is presented. The circuit compensates for pixel transconductance mismatch in addition to offset error via analog to digital conversion reference current scaling. Hspice simulations using parameters of a 0.35 /spl mu/m CMOS process illustrate the advantage of the new technique over usual correlated double sampling (CDS) in current mode sensors. Parallel integrated analog to digital converters (ADC), a data line-buffer and digital control complete the circuit making data transmission easy and simplifying hardware needed for using the image sensor.

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

In this paper we describe a novel PLL circuit design. The proposed topology is based on two loops: the conventional fine loop and a new coarse loop. The fine tuning loop which includes a phase-frequency detector, a charge pump and a differential voltage controlled oscillator (unity feedback PLL) is rather slow. However the coarse tuning loop reacts faster and accelerates convergence. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained, as well as a lower sensitivity to power supply variations.

In this paper, a current tuneable fully differential transconductor cell (GM-C) dedicated for filtering applications is proposed. The architecture of this cell is based on a cross-coupled differential pairs input stage with folded cascode output stage in order to realise a high DC gain integrator. The resulting integrator's architecture tolerates fabricated characteristic deviations from an ideal representation and has been selected to give a simple tuneable integrator which allows the full programmability of the designed filter. Also, the realisation of a generic 4-order bandpass filter is presented with the 3.3 volts 0.35 /spl mu/m CMOS technology available through the Canadian Microelectronics Corporation (CMC). Finally, principal deviations from ideal transfer function will also be discussed in order to evaluate possible effects of the frequency response introduced by a non ideal integrator.

Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGAs is presented. The FFT core for 1024 complex data point is implemented on the X-CIM which is a Re-configurable Acceleration Subsystem (RAS) with a TMS320C4x DSP-processor and two XC4013 FPGA as its processing units. The proposed FFT machine is an alternative to the bit serial-parallel FFT algorithm using Distributed Arithmetic Look Up Table (DALUT) method. The advantage of proposed design is mainly in its cost effective and hardware-efficient parallel implementations of the N-point DFT, offering highly attractive throughput rates in relation to the conventional DSP processors. Moreover, the processor's data-path structure is independent of sampled data-paints, and it has a self-sorting property where the output is in properly ordered form. Our goal is to improve size-performance requirements of an FFT core function using modular and hierarchical VHDL description combined with IP-core library elements from Xilinx.

In this paper, built-in self-test (BIST) approach has been applied to test digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, integral nonlinearity (INL), and differential nonlinearity (DNL) errors and monotonicity are tested without using mixed-mode or logic test equipment. An off-line calibrating technique has been used to insure the accuracy of BIST circuitry and to reduce area overhead by avoiding the use of high quality analog blocks. The proposed BIST structure presents a compromise between test cost, area overhead, and test time. By a minor modification the test structure would be able to localize the fail situation. The same approach may be used to construct a fast low cost off-chip D/A converter tester. The BIST circuitry has been designed and evaluated using complementary metal-oxide-semiconductor (CMOS) 1.2 /spl mu/m technology.

A new CMOS transconductance (Gm) circuit with voltage-tunability and very wide bandwidth is proposed and analysed. The transconductance circuit is then used to realize a tunable VHF 2nd-order bandpass filter cell. The center frequency (f0) of the designed filter can be tuned by varying the transconductance value (gm) of the tunable Gm circuit. Simulation results indicate the excellent performances of both the transconductance circuit and the filter over a wideband range. The transconductance value can be tuned from 40 /spl mu/S to 950 /spl mu/S (490 /spl mu/S) and the filter center frequency (f0) in the range 30 MHz (4 MHz)-110 MHz (49 MHz) for /spl plusmn/2.5 V (/spl plusmn/1.5 V) supply voltages.

A new generation of remote control to be used with an implantable neural stimulator is described. The device incorporates a Motorola 68HC805C4 microcontroller, a data encoder, an AM modulator, an alphanumeric LCD, a keyboard, and a RS-232 line driver. PEPU (processeur externe pour prothese urinaire) was developed to miniaturize the existing controller based on an IBM-PC-compatible computer. The present software version of PEPU can control all the prostheses made with the MA4200 integrated circuit.>

A fully programmable digital speech processing system for deaf patients is described. Speech coding is based on vector quantization. The system simulates in real-time the characteristics of a 10-channel tactile vocoder. The system is based on three chips: a Codec TCM29C13, a DSP digital signal processor TMS320E17, and a full custom integrated BiCmos circuit. The architecture of this portable, low-power unit allows a market improvement in synthetic vowel discrimination.>

An integrated circuit intended for neural stimulation applications is described. The device has been designed and implemented in CMOS 3- mu m technology. The major advantages of the chip are its programmability and versatility. The intensity, format, and timing of the current pulses available at the eight channel outputs are serially and fully programmable. The different components of the device are controlled by a finite-state machine implemented by a PLA (programmable logic array). This implant can be placed inside the human body for long-term neural stimulation, and it can be used for many neurologic stimulation applications with minor modification of the implant.>