Radiation-induced degradation poses a critical challenge to the reliability of space-grade integrated circuits (ICs). Existing radiation-aware models largely remain at the device level and lack direct integration with circuit or system design flows, limiting their practical use in radiation-aware IC design. To address this, this work proposes Ramen, a non-invasive radiation-aware device modeling framework that is fully compatible with commercial Process Design Kits (PDKs). Ramen accurately captures total ionizing dose (TID) and displacement damage dose (DDD), enabling early-stage evaluation at both circuit and system levels without requiring modifications to existing PDK structures. By seamlessly integrating with standard analog, mixed-signal, and digital flows, the radiation-aware models not only support SPICE-based circuit simulation but also feed into standard library characterization tools to generate radiation-aware Liberty libraries. These libraries encode dose-dependent timing, leakage, and power information, allowing radiation effects to be captured in synthesis, timing analysis, and back-end implementation. Experimental validation on a 180 nm CMOS imager under radiation stress shows that the proposed framework achieves <15% simulation errors for both analog and logic circuit, confirming the reliability of Ramen for radiation-aware IC design.

Fault simulation is essential for transient fault analysis, yet it is extremely time-consuming. Fault propagation depends on signal logic values and their correlations with circuit logics. This paper proposes a Transformer-based architecture for fault propagation modeling to predict fault propagation outcomes at the register-transfer level (RTL). For the proposed method, we encoded logic values of all signals of the circuit with two-layer embeddings and fault injection information to construct the model’s input token sequence. The self-attention mechanism of Transformer is responsible for capturing intersignal dependencies. The training dataset is collected from the PicoRV32 RISC-V core through traditional bit-level fault simulation. Experimental results show that the proposed model achieves an average propagation accuracy of 99.78% on the training group and 97.68% on the testing group (unseen benchmarks), with a speedup ranging from $677 \times$ to $3044 \times$ compared to RTL simulation. The proposed approach provides a scalable and efficient solution for accelerating transient fault analysis.

For reliability-critical silicon systems, transient errors caused by cosmic rays necessitate comprehensive and efficient reliability analysis before product deployment. Fault injection (FI) serves as a cost-effective alternative to expensive irradiation experiments for evaluating system robustness. However, simulation-based FI is constrained by the performance of the underlying hardware platform, making it impractical for large-scale designs, where achieving high fault coverage can take months or even years. Furthermore, most transient errors have no impact on system functionality, and filtering out these insignificant errors in advance can significantly enhance the efficiency of reliability analysis. To address these challenges, we propose Tenpura, a fault evaluation platform designed for ultra-fast reliability analysis. In Tenpura, a transient fault scope narrowing method is introduced to narrow the FI scope via the proposed scan-based activity tracing flow, further optimizing fault analysis and improving overall efficiency. By leveraging FPGA emulation and scan chain-based fault analysis at the pre-silicon stage, Tenpura achieves high-efficiency fault reduction (88.49–96.26% across three design under tests (DUTs) including RISC-V cores and NVDLA-based AI accelerator) within one month, delivering over an order of magnitude faster fault analysis compared to SOTA methods.

Battery management system (BMS) is a key component to keep battery packs operating in safe and enduring conditions. This paper presents a SystemC-AMS–based BMS simulation platform including both BMS control and cell modeling designed to support fault injection and modular protection analysis. Through single-bit fault injection experiments, only a small fraction (12.8%) of injected faults violate the safety conditions. And SOC estimation and ADC modules are identified as the most critical components with faults covering all severe conditions such as overcharge, overdischarge and overheating. After applying dual module redundancy (DMR), we can enhance the reliability and reduce safety violations from the original 92321 errors to 72020 and 7860 errors or 78.01% and 8.51%, respectively for ADC and SOC modules. With DMR protection for both the ADC and SOC modules, we can eliminate all safety violations.

Reliability-demanding devices often require numerous fault injections (FIs) for reliability analysis in the product cycle. However, software-based FI typically demonstrates extremely low efficiency due to low simulation throughput, especially for large-scale designs, while hardware-based FI presents challenges related to complexity of setup and limited scalability. Additionally, FIs often occur in intervals where errors do not affect the system’s outcome, e.g., after final read before next write, necessitating efficient pruning of non-impactful FIs. To address this, a general-purpose FI-specialized framework, Genshin, is proposed for rapid reliability analysis. On the hardware side, we provide an FI-specialized design, which works with Design Under Test (DUT) chips on PCB boards and supports FI control based on the scan chain (SC). An integrated programmable logic allows for flexible and custom FI pattern definitions. Furthermore, an architecturally correct execution (ACE) analysis generates pruned fault tables for DUTs. In Genshin, the SC logic achieves 3,802-65,388 cycles/FI across SC lengths ranging from 2,795 to 61,393 in different DUTs, while the programmable logic enables custom error patterns such as layout-aware multi-bit upset (MBU). Furthermore, the pruned fault tables achieve fault reduction rates from 45.80% to 83.21%.

Spiking Neural Networks (SNNs) implemented with Resistive RAM (ReRAM) offer promising advantages in area and power efficiency due to their compatibility with compute-in-memory architectures. However, process-induced resistance variability in ReRAM cells poses a significant challenge to inference accuracy. To address this issue, we propose a test and calibration framework to maintain target model accuracy. The test flow employs systematic pattern generation and formulates a set of linear equations to estimate ReRAM cell resistances. Given the estimated resistance values, rows exhibiting large deviations are replaced using redundant rows to mitigate computational errors. Experimental results on Tiny ImageNet with a Transformer-based SNN demonstrate that the proposed calibration method improves inference accuracy by 2.3% and 4.2% with one and two redundant rows, respectively.

In this paper, we proposed a novel probabilistic fault propagation method for circuit of the register transfer level (RTL), enabling early-stage fault injection analysis. For the proposed method, we formulate and compute the probability of fault propagating to the output of an RTL operator based on the input logic patterns. By computing the probability of operators level by level (keeping correct circuit evaluation order), we can estimate the propagation probability at destination registers for each injected fault. By the probabilistic propagation list, we can then construct a propagation graph for multi-cycle analysis to avoid lengthy fault simulations.In our experiments, the proposed method can have a speedup of 35X to 158X faster than a traditional fault injection method, while achieving an average of 94.94% accuracy in the prediction of propagation of an injected fault. Hence, the proposed method can be applied to select high-quality fault candidates and to quickly evaluate the reliability of different design choices.

Debugging is becoming increasingly important to identify functional errors of SoC caused by transient faults and to ensure system reliability. However, due to the complexity of a SoC, locating faulty signals and cycles can be challenging. Debugging flow and tool, e.g., EQED [1], applies signature blocks (MISR circuits) to capture errors and uses bounded model checking to identify transient fault candidates. In this paper, we proposed a reduction method to select essential signals for inserting and connecting signature blocks. The method identifies the propagation condition of faults and constructs a fault propagation graph (a tree of equivalent propagated faults) for the selection of essential transient faults. In our experiments of a RISC-V core, we can reduce the selected signals to about 2% on average, while maintaining more than 99% of debugging coverage.

In order to facilitate the deployment of diverse deep learning models while maintaining scalability, modern DNN accelerators frequently employ reconfigurable structures such as Network-on-Chip (NoC) and multi-level on-chip memory hierarchy. To achieve high energy efficiency, it is imperative to store intermediate DNN-layer results within the on-chip memory hierarchy, thereby reducing the need for off-chip data transfers to/from the DRAM memory.Two well-established optimization techniques, node fusion and loop tiling, have proven effective in retaining temporary results within the on-chip buffers, commonly used to minimize off-chip DRAM accesses. In this paper, we introduce MultiFuse, an infrastructure designed to automatically explore multiple DNN layer node fusion techniques, enabling optimal utilization of the on-chip multi-level memory hierarchy.Experimental results demonstrate the effectiveness of our retargetable infrastructure, which outperforms Ansor’s algorithm. Our exploration algorithm achieves a remarkable 70% reduction in Energy-Delay Product (EDP) while gaining a 67x speedup in search time when executing the data-intensive MobileNet model on a single DNN accelerator.

There are several applications of functional simulation with transient faults including evaluation of the vulnerability and design error-tolerant measures, as well as debugging of electrical hardware issues. Yet, the simulation is extremely slow given the complexity of RTL circuits and a large number of transient faults proportional to the total execution cycles. Recently, fault reduction methods are developed with Architecturally Correct Execution (ACE) analysis. The method can identify only about 3 % of total faults deemed necessary for simulation. However, the analysis effort is still non-trivial and most of the time is consumed in the small single-cycle fault simulation. In this paper, we proposed to use FPGA emulation to speedup the above process. In the experiments, on a RISC- V core, for a set of 16K faults, the analysis time are reduced from 1 hours to 1min, On average, the fault emulation has a speed up factor of 60 compared with a software implementation.

Welcome to the 31th Asian Test Symposium (ATS 2022). Since 1992, ATS has been held every year in various Asian cities as the largest symposium that focuses on testing of integrated circuits and systems. Many researchers and engineers from all over the world have attended the past symposia and enjoyed discussions. After more than two years of COVID-19 pandemic, ATS 2022 is being held as a hybrid event to invite symposium participants to join on-site meeting, and also to allow on-line participation through conference app platform.

To satisfy requirements of system reliability, the importance of debugging grows increasingly to identify functional errors of SoC caused by transient faults. Yet, due to the complexity of a SoC, efforts to locate faulty signals and cycles are also dominating the yield ramp up period. Debugging-assisted circuits and associated tools play an essential role to keep the costs down. Notably, QED [1] and EQED [2] methods can use observation points, hardware checkers, and MISR to limit the candidate faulty cycle range and to prove the faulty signal candidates through bounded model checking (BMC). In this paper, we proposed a transient fault list reduction method as a filter before we apply BMC to check the validity of faulty signals and cycles. The method identifies the propagation condition of faults and constructs a set of fault traces (a tree of equivalent propagated faults) to examine and classify the transient faults. The roots found in the fault traces can significantly reduce possible faulty candidates to check with BMC. In our experiments of a RISC-V core, we can reduce the time spent on BMC from 97 hours to 6 hours of simulation and graph analysis on average. Overall, we can reduce the initial faulty candidates to under 5% or less of original list.

It is essential to perform extensive RTL functional fault simulation for critical systems in order to analyze the vulnerability and design error-tolerant measures accordingly. Since the number of faults would be exceedingly large for a full simulation, fault sampling techniques are applied. However, little information are available for fault characteristics, so the sampling might not be effective: often producing no error output or similar output syndromes.In this paper, we utilized an advanced Architecturally Correct Execution (ACE) analysis to study the functional fault characteristics of registers on a RISC-V core. From the results for all registers, only less than 0.34% to 2.76% of total faults need to be simulated. We then further sample and simulate these remained faults at RTL to analyze the categories for failure output syndromes. We found that faults at non-architecture registers have much higher masked results (as high as 90%), as compared with architecture registers (16% – 40%). Therefore, it is suggested that fault sampling should consider register and fault characteristics for a more effective result.

Critical systems require extensive simulation effort with functional fault injection on RTL circuits during design stages in order to analyze vulnerability and engineer error-tolerant measures accordingly. Yet for a complex SoC, long simulation cycles are necessary for each injected fault. Therefore it is imperative to prune as many faults as possible to improve simulation efficiency and turn-around time for designers.In this paper, we propose a novel method (ACE-Pro) to reduce the functional fault list. The method extends architecturally correct execution (ACE) analysis by creating a propagation graph, where a node is a fault marked with an ACE bit at a cycle and a directed link between nodes represents the propagation condition to another register at the next cycle. By checking and propagating through the graph the properties of masking (a fault is masked by logic on its propagation path to next registers) and singly-equivalence (a fault is covered by another fault on the next register), we show fault reductions by 98.91% to 99.91% (49.2% to 88.4% from the reduced faults in Equivalent Regions) in our experiments on a RISC-V core.

Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.

Optical flow algorithm, which estimates the motion detection of consequent video frames, is widely used in surveillance system, Advanced Driver Assistance Systems (ADAS) and object movement estimation in scene analysis. Among different optical flow algorithms, Farneback version provides a better accuracy and brightness-change-resistant displacements by estimating the flow from polynomial domain rather than intensive maps. However, high computation complexity and inconsistent data access patterns make it difficult to be implemented on a hardware platform. In this work, we present a micro-architecture design of Farneback optical flow, which is flexible for optimization with high level Synthesis (HLS) tools. The original software-based implementation was decomposed into functional blocks to balance latency of different stages and flows of data were rearranged to accommodate better memory access patterns. The data flow arrangement is based on a proposed backtrace mechanism, where DRAM accesses of polynomial coefficients in current frame makes consistent traffic patterns, and therefore make it possible to integrate more functional blocks into a deeper pipeline. For several micro-architecture design versions, we demonstrate options of fixed and floating points, optimization techniques such as multiple DMAs and different levels of pipeline integration. We implemented our design on Zedboard Mini-ITX 7045. The results show a 17x end-to-end speedup against a naive HLS version with an image size of 160x120. Considering only the hardware-accelerated part, our FPGA implementation is 40x faster than the naive HLS version with only 50% of the FPGA hardware resources.

Aging as a reliability parameter is often tested with elevated temperature or supply voltage (burn-in) environment, which is expensive and may damage product in the process. It has been found that circuit aging is primary due to signal stress conditions. And the aging effects will manifest on long critical paths for induced extra delays. In this paper, we proposed a test flow to predict timing-failure age caused by Negative-Bias Temperature Instability (NBTI). First, the flow measures critical path delays (which may variate due to process variation). Given the tested path delays, we sample a batch of delay profiles of cells on tested paths. Next, we simulate above delay profiles with known signal stress conditions (from functional simulation) to predict the failure age. In experimental results, comparing with reference golden sample (with known ages), we can obtain a very close prediction of failure ages (<;5% of errors).

We present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our hardware-independent software layer, applications built on top of the fast virtual platform can be executed seamlessly on the prototype. The emulation result justifies the effectiveness of our processor architecture in embedded applications.

Network-on-chip (NoC) can be a simulation bottleneck in a many-core system. Traditional cycle-accurate NoC simulators need a long simulation time, as they synchronize all components (routers and FIFOs) every cycle to guarantee the exact behaviors. Also, a NoC simulation does not benefit from transaction-level modeling (TLM) in speed without any accuracy loss, because the transaction timings of a simulated packet depend on other packets due to wormhole switching. In this paper, we propose a novel NoC simulation method which can calculate cycle-accurate timings with wormhole switching. Instead of updating states of routers and FIFOs cycle-by-cycle, we use a pre-built model to calculate a flit's exact times at ports of routers in a NoC. The results of the proposed simulator are verified with NoC implementations (cycle-accurate at RTL) created by a commercial NoC compiler. All timing results match perfectly with packet waveforms generated by above NoCs (with 40-325 times speed up). As another comparison, the speed of the simulator is similar or faster (0.5-23X) than a TG2 NoC model, which is a SystemC and transaction-level model without timing accuracy (due to ignoring wormhole traffics).

System tests with boards are applied to capture defects in functional modes. Yet, these tests are usually costly with limitation on the production throughputs. Stressed structural tests (patterns produced by traditional ATPG) have been proposed to correlate with system tests and to replace them in production. However, due to low confidence level (small experimental samples and volatile chip variability conditions), we need a process to tune and apply stressed tests gradually. In this paper, we use SVM to classify stressed tests with the goal to select high-quality chips without the need of further system tests. The remaining (smaller batch of) chips will be processed by system tests for further defect screening. The proposed SVM method can be flexible in tuning the relative size of chip partitions.

New generations of display technologies provide a significantly improved dynamic range compared to conventional display devices. Inverse tone mapping methods have been proposed to convert low dynamic range (LDR) images to HDR ones, and several of them require multiple exposure LDR images of the same scene as inputs. However, the vast majority of LDR images and videos available have only one single exposure. In this paper, we propose a region-based enhancement of the pseudo-exposures to generate an HDR image. First, we present an exposure dependent curve to convert one LDR image to the pseudo-multiple-exposures. Only certain regions of the pseudo-exposures contain noticeable detail information. We propose a region-based enhancement on the pseudo-exposures to boost details in the most distinct region. Thereby the region-enhanced pseudo-exposures are fused into an HDR image. The fused image thus enhances details in the bright region of the dark image and the dark region of the bright image. Compared with other inverse tone mapped methods, our method generates lower total contrast error measured under the dynamic range independent image quality assessment method in [1].

Process variation in advanced CMOS processes is an increasingly important influence in test efficiency, design optimization and yield learning. Yet, there is no efficient test process to assist designers to categorize chips for analyzing the influence of variation on their respective objectives. In this paper, we propose a test process and an analysis method with multiple clocks. Each chip is first tested with selected paths on multiple clocks (smaller than target chip clock). And the test results of outputs on selected paths are recorded and further used as a signature to determine the class of which the chip belongs to. As an application, we use the proposed scheme to sort chips into different categories and assign a supply voltage configuration for each category to fix chip timings. In experiments, results show that testing with one or two clocks, the method can obtain chip yields of 88-99% (original yield is 9-34%) with an increase of 4-25% nominal dynamic powers, while full-swing voltage setup would require 50% increase of powers.

Process monitoring circuitry such as ring oscillators or delay-test-based diagnosis method has been applied to characterize process variations of a chip. For a design process, it is also desirable to consider circuit features that might cause such a systematic process variation. In this paper, we use the variation map built from measured excessive delays to analyze the correlation between circuits and systematic variations. With support vector regression, a physical map of a circuit is partitioned into different regions that are inherently affected by similar causes. And then possible features (e.g., cell types, layout characteristics, etc.) that influences these regions are ranked. Experimental results show that the proposed method can effectively identify process regions and rank major features at top orders with injected variations.

Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability.

There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.

Process variation comes from several aspects during IC manufacturing, resulting in tremendous yield loss in advanced CMOS process. Recently, post-silicon tuning techniques that could adaptively manipulate failed chips to compensate the variations have been widely studied. Yet, full-chip adjustments can also increase dynamic and leakage power consumption. A fine-grain voltage-control architecture was proposed to tune only necessary parts of circuits. The corresponding diagnosis and tuning algorithm, however, require variable test clock strobing to measure path delays, which incurs a large test cost. In this paper, we propose to build a test data library that only uses a few fixed test clocks. We can then use the library to categorize the test results and sort the chips into different correction voltage tuning configurations. The experimental results show that with much lower cost (4% in average), the method can fix from 86%to 118% chip samples as compared to a satisfiability (SAT)-based method that requires accurate path delay measurement.

TurboVG is a hardware accelerator for the OpenVG 1.1 library that operates sixteen times faster than an optimized software implementation. This improved efficiency stems from a well-designed hardware-software interaction capable of handling massive data transfers across hierarchical layers without performance loss. By combining multiple TurboVG cores, the library can support screen resolutions of up to Full-HD 1080p.

A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays or tuning down on fast cells to save power. On our test cases, we can correct up to 75% of failed chips to pass performance tests, while maintaining less than 10% increase over nominal power consumption.

This work presents a low-cost wireless system design that serves as an interface to support the SoC with contactless testability feature. The communication hierarchy includes PHY, MAC, data exchange, and test wrapper functions. The wireless does not require external antennae and crystal reference, and therefore minimize the setup cost. The embedded all-digital timing generation achieves robust performance in the noisy environment. The whole wireless system occupies a small area. In a 0.18μm device-under-test, the active area of wireless front-end is 0.14mm2 and the gate count for digital processing is 112K. The maximum energy efficiency for uplink is 1.1nJ/bit and for downlink is 2.9nJ/bit when the wireless distance is set around 1cm. The prototype system includes test equipment and an SoC as the device-under-test. The SoC integrating logic, memory, and analog plug-in modules can be contactlessly tested. It is a low-cost platform controlled by a simple hand-held computer.

Test integration for heterogeneous cores under test has been a challenging problem in a system-on-chip (SoC) design. To integrate heterogeneous cores under test, the test wrapper should be capable of dealing with multiple-clock domain problems, at-speed testing problems, test power problems, etc. In this paper, we propose an alternative wrapper architecture that supports multiple clock domains, and therefore test operations can run (test) at system speed. Since each CUT has very different requirements, the test wrapper unavoidably needs to be re-designed for a new CUT. In order to reduce the manual effort, we propose to automatically generate test wrappers and the corresponding test programs based on the given configuration and test description for each CUT. We adopted the IEEE 1450.6 standard, a.k.a. Core Test Language (CTL), as the test description language in this work. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. We have successfully integrated a test wrapper generated by using our tool into a test chip which includes a Memory BIST and a Logic BIST and tapped out the chip in TSMC 0.18$\mu$m technology. The experiments showed that the area overhead of proposed architecture is only 0.02\% of chip area in the chip.

Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation method for gate or interconnect delays based on the maximum likelihood estimation. The proposed method outputs most probable gate/interconnect delays that matches the measured path delays under the nominal delay distribution. Unlike the previous diagnosis methods, our method does not take any assumption on defect numbers, sizes and types (models), and thus it can be used to diagnose performance bottlenecks resulted from systematic variations. The experimental results show that the average correlation achieves 0.848 between estimated (by the proposed method) and sampled segment delays (generated from process models) for ISCAS89 benchmarks. There is a substantial improvement of 0.271 over the existing method.

Test patterns of path delay faults (PDFs) are usually generated with static or robust sensitizing criteria for side inputs of gates, because defects affecting the delays of the PDFs will be captured by these patterns unconditionally. However, under functional sensitization (FS), there exist a class of defects that can be tested unconditionally, if they are not masked by the off-input controlling values. In this paper, we propose a new pattern generation method for functionally sensitizable PDFs to improve the detectability of defects. It is shown in the experiments that with the proposed method, extra segments (up to 24.02% for one benchmark) of critical paths become testable compared with only robust/non-robust patterns.

With continuing trends to embed more on-chip test circuits, increasing complexity requires more efforts on design and validation. In this paper, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. In our experiments, 30% to 50% total costs are saved compared to an initial ad-hoc setup.

Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.

Systematic variations with device parameters and critical dimensions are crucial information in achieving higher yields with semiconductor devices. In this paper, we propose a method to extract systematic variation models of segment delays based on the measured path delays of tested chips. First, we cluster chips according to the similarity of the path delay vectors. Then, for each cluster, a hierarchical variation model is built. The extracted models are closely related to the design and can have many potential applications for yield and quality enhancements.

Automatic test pattern generation (ATPG) for path delay faults is an essential tool for structurally testing performance problems of circuits. The complexity issues of an ATPG are often due to the large number of selected target paths and assorted ways to sensitize these paths. In this paper, we tried to address the later problem by applying a SAT solver. First, we introduce a SAT model (CNF formats) for all sensitization criteria: robust, non-robust and function-sensitizable. Then, to ease the problem of re-constructing the circuit for every criteria in the SAT solver, we proposed to unify all sensitization under the same model. We also found that we could further save efforts of re-building the SAT model for every paths by sharing constraints. Applying the above techniques, we could achieve 10-1000 times of speedup for most benchmark circuits.

Traditionally, diagnosis methods use static models for delay defects, while there exists a class of faults including cross-coupling capacitance and resistive shorts exhibiting different effects on path delays with different input patterns. Blindly treating such faults will lead to skewed results for locating defects. In this paper, we discuss the method to handle these faults without explicitly modeling each type of faults. In the process, we differentiate failed delay paths into two categories: static and pattern-dependent. We further explore these information to list possible candidates (including coupling defects) causing timing failures for further analysis. The experimental results show that average rankings of suspects are 2.1 and 4.6 for failing segments and coupling pairs, respectively.

It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target path can then be validated through simple calculation. Yet, no decomposition process is available to find paths that satisfy the above property. In this paper, given a set of target critical paths, we propose a two-stage method to find a set of robust-testable paths (with smaller number than the original set). The first stage constructs a necessary subset for critical robust paths, and the second stage identifies remaining functional sensitizable segments and their corresponding composing robust paths. The experiments show that a large percentage (several benchmarks close to 100%, 75% on average) of critical paths can be covered for most circuits. All paths and coverage are verified to match the best possible results. The data also indicate that the remaining hard-to-test (functional sensitizable) paths actually result from only a few tens of segments in the circuit (except for one circuit, s35932). DfT technique can then be applied to these uncovered segments for full testability with small overheads.

Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we proposed a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the above linear constraints with a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. In the diagnosis framework, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. In the experimental results, for most cases of injecting 10% of the longest paths delays, the probabilities are over 90% for locating faulty segments within the list of top-ten candidates, and the average rankings are among the top 5 suspect locations.

In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.

Critical path selection is an indispensable step for testing of small-size delay defects. Historically, this step relies on the construction of a set of worst-case paths, where the timing lengths of the paths are calculated based upon discrete-valued timing models. The assumption of discrete-valued timing models may become invalid for modeling delay effects in the deep submicron domain, where the effects of timing defects and process variations are often statistical in nature. This paper studies the problem of critical path selection for testing small-size delay defects, assuming that circuit delays are statistical. We provide theoretical analysis to demonstrate that the new path-selection problem consists of two computationally intractable subproblems. Then, we discuss practical heuristics and their performance with respect to each subproblem. Using a statistical defect injection and timing-simulation framework, we present experimental results to support our theoretical analysis.

Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.

In this paper, we propose a new methodology for diagnosis of delay defects in the deep sub micron domain. The key difference between our diagnosis framework and other traditional diagnosis methods lies in our assumptions of the statistical circuit timing and the statistical delay defect size. Due to the statistical nature of the problem, achieving 100% diagnosis resolution cannot be guaranteed. To enhance diagnosis resolution, we propose a 3-phase diagnosis methodology. In the first phase, our goal is to quickly identify a set of candidate suspect faults that are most likely to cause the failing behavior based on logic constraints. In the second phase, we obtain a much smaller suspect fault set by applying a novel diagnosis algorithm that can effectively utilize the statistical timing information based upon a single defect assumption. In the third phase, our goal is to apply additional fine-tuned patterns to successfully narrow down to more exact suspect defect locations. Using a statistical timing analysis framework, we demonstrate the effectiveness of the proposed methodology for delay defect diagnosis, and discuss experimental results based on benchmark circuits.

In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timing information based upon single defect assumption. We evaluate its performance and its applicability to single as well as multiple defect scenarios via statistical defect injection and simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concept in statistical delay defect diagnosis, and discuss experimental results using benchmark circuits.

The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In this paper, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure. We apply the proposed path selection technique for selection of a set of paths for dynamic timing analysis considering power supply noise effects. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored. Thus, they indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

In current industrial practice, critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. The assumption of discrete timing models can be invalidated by delay effects in the deep sub-micron domain, where timing defects and process variation are statistical in nature. In this paper, we study the problem of optimizing critical path selection, under both fixed delay and statistical delay assumptions. With a novel problem formulation and new theoretical results, we prove that the problem in both cases are computationally intractable. We then discuss practical heuristics and their theoretical performance bounds, and demonstrate that among all heuristics under consideration, only one is theoretically feasible. Finally, we provide consistent experimental results based upon defect-injected simulation using an efficient statistical timing analysis framework.

In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.

We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for cell-based designs with all cell delays modeled as random variables. Our algorithm propagates probabilistic timing events through the circuit and obtains final probabilistic events (distributions) at all nodes. The new algorithm is deterministic and flexible in controlling run time and accuracy. However, the algorithm has exponential time complexity for circuits with reconvergent fanouts. In order to solve this problem, we further propose a fast approximate algorithm. Experiments show that this approximate algorithm speeds up the statistical timing analysis by at least an order of magnitude and produces results with small errors when compared with Monte Carlo methods.

Increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and distributed delay variations lead to increased signal integrity problems in deep submicron designs. These problems can cause logic errors and/or performance degradation and must be addressed both in the design for deep submicron and testing for deep submicron phases. Existing delay testing techniques cannot capture the effects of noise on the cell/interconnect delays. In this paper, we address the problem of delay testing considering crosstalk-induced delay effects. We propose solutions for target fault selection and pattern generation. The key elements of our strategy are performance sensitivity analysis with respect to crosstalk noise and a genetic algorithm (GA) based vector generation technique. The role of performance sensitivity analysis is to consider the effects of crosstalk noise during the target fault selection process. Next, for each selected fault consisting of a path and a set of crosstalk noise sources interacting with the path, we apply our iterative GA-based pattern generation process. Our goal is to derive a test that produces a large crosstalk-induced delay effect on the given path. Our technique allows consideration of any number of coupling sources along the target path. Due to its flexibility, efficiency and scalability, the technique can be applied to large circuits.

The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. We propose a statistical framework for analyzing the performance sensitivity of designs to various timing related defects/noise/variations. The core engine of our approach is a highly efficient statistical timing analysis tool. We describe the application of our framework for delay fault modeling and analysis of resistive opens and shorts and as well as interconnect crosstalk. We present experimental results demonstrating the accuracy of our statistical framework as compared to SPICE (for a given set of input patterns) and nominal worst-case analysis. Experimental results for analysis of resistive opens and shorts are also included.

Noise effects such as power supply and crosstalk can significantly affect the performance of deep submicron designs. These delay effects are highly input pattern dependent. Existing path selection and timing analysis techniques cannot capture the effects of noise on cell/interconnect delays. Therefore, the selected critical paths may not be the longest paths and predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a path selection technique that can consider power supply noise effects on the propagation delays. Next, for the selected critical paths, we propose a pattern generation technique for dynamic timing analysis such that the patterns produce the worst-case power supply noise effects on the delays of these paths. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered vs. when these effects are ignored. Thus, they validate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.

The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in nature. In order to capture the effects of these statistical variations on circuit performance, we incorporate statistical information in timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. We further propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure caused by the target type of defect, noise or variation source. This new path selection methodology defines a new path/segment searching paradigm for detecting delay faults in deep sub-micron devices.