The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand-alone and embedded applications where the combination of non-volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub-20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant-on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.

This paper presents an innovative architecture for radiation-hardened FPGA (Field Programmable Gate Array). This architecture is based on the use of MTJs (Magnetic Tunnel Junctions), magnetic nanostructures used as basic elements of MRAM (Magnetic Random Access Memory). These devices are totally immune to radiations and can be used as a reference memory to perform "scrubbing" techniques, which consist in regularly reloading the configuration of the FPGA to fix the radiation induced errors that may have occured. This approach allows hardening the circuits at low cost in terms of area, while reducing the standby power consumption and offering new fonctionalities, like dynamic reconfiguration. A silicon demonstrator was implemented, including a 2-inputs LUT (Look Up Table) and tested using a digital tester, giving encouraging results.

Future embedded systems are going to be more sensitive to hardware faults. In particular, intermittent faults are going to appear faster in future technologies. Understanding the occurrence of faults and their impact on systems and applications can help to improve the fault-tolerance of systems. However, there is no study on their effects in more complex digital circuits. We propose an experimental platform for accelerating and catching the occurrence of intermittent faults in complex digital circuits. We experimentally show that intermittent faults can appear during the lifetime of the circuit, very early before the wear-out period. We studied the impact of processor activity on intermittent faults rate. We conclude that a continuous usage of circuits causes the occurrence of intermittent faults earlier than a low usage under identical operating conditions. We show that applications do not have the same sensitivity to intermittent faults.