Demo Data from VLDB 2026 / reviewers in the wild / expert
A. Matsushita
dblp:180/3393
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1966
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 62% Integrated circuit design · 19% Emerging computing paradigms · 19% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
magnetic memory |
0.0 | 1 | 1966 | Woven Wire Memory for NDRO System · IEEE Trans. Electron. Comput. 1966 |
Integrated circuit design
memory circuit design |
0.0 | 1 | 1966 | Woven Wire Memory for NDRO System · IEEE Trans. Electron. Comput. 1966 |
Emerging computing paradigms
noise mitigation |
0.0 | 1 | 1966 | Woven Wire Memory for NDRO System · IEEE Trans. Electron. Comput. 1966 |
Methods — techniques the papers use, named apart from their topics
two-memory-cell per bit · 0.0diode-transformer matrix driving · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1966 | Woven Wire Memory for NDRO SystemabstractA 4096 word NDRO memory system using the high speed woven wire memory is discussed. The operating principle and the NDRO characteristics of the memory together with stack construction, noise problems, circuitry, and experimental results are explained. The memory weave consists of electroplated magnetic thin-film wires for the digit-sense lines and insulated wires for the word lines, which are mounted on a terminal plate to form a plane. The stack is made up of 32 planes. To minimize noise effects, the word lines are diode-transformer matrix driven and the two-memory-cell per bit method is used in the digit-sense lines. The memory capacity is 4096 words × 10 bits. Cycle times of 400 ns for read and 600 ns for write, respectively, were achieved with high operating stability. H. Maeda, A. Matsushita, M. Takashima |
IEEE Trans. Electron. Comput. | 2 |