This paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. The results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

Memristor-based crossbars are considered to be promising candidates to accelerate vector-matrix computation in deep neural networks. Before being applied for inference, mem-ristors in the crossbars should be programmed to conductances corresponding to the network weights after software training. Existing programming methods, however, adjust conductances of memristors individually with many programming-reading cycles. In this paper, we propose an efficient programming framework for memristor crossbars, where the programming process is partitioned into the predictive phase and the fine-tuning phase. In the predictive phase, multiple memristors are programmed simultaneously with a memristor programming model and IR-drop estimation. To deal with the programming inaccuracy resulting from process variations, noise and IR-drop and move conductances to target values, memristors are fine-tuned afterwards to reach a specified programming accuracy. Simulation results demonstrate that the proposed method can reduce the number of programming-reading cycles by up to 94.77% and 90.61% compared to existing one-by-one and row-by-row programming methods, respectively.

The charge-redistribution data converter topology is constructed from an array of parallel-connected capacitors with a specific capacitor ratio, and is a fundamental component of successive approximation register (SAR)-analog-to-digital converter (ADC) architectures. This paper presents complementary placement and routing algorithms for such capacitor arrays with the goal of nonlinearity minimization in the target SAR-ADC architecture. Starting from a state-of-the-art static nonlinearity model and its accompanying placement method, generalizations are made for both binary- and nonbinary-weighted capacitor ratios. Taking the generalized nonlinearity model and capacitor routing complexity into consideration, an improved placement method was developed, augmented with a matching-based routing technique driven by routing length adjustment. Analytical results compare the new methodology to the state-of-the-art, achieving superior resolution, linearity, and area.

MEMS-based sensor circuits are traditionally designed separately using CAD tools specific to each energy domain (electrical and mechanical). This article presents a complete approach for combined MEMS-IC robustness optimization. Advanced methods for robustness analysis and optimization considering design, operating and process parameters, developed for integrated circuits, are transferred to MEMS-IC systems. Both electrical and mechanical design and process parameters are included in the optimization. The methodology is exemplified on two demonstrator examples: a MEMS microphone and a MEMS accelerometer, each with an integrated readout circuit. A successful optimization requires the simultaneous inclusion of design parameters and process tolerances from both energy domains. To save CPU time, a reduced-order, circuit-level model is used for the MEMS part and this model is created only when necessary. To integrate the generation of the simplified model into the optimization flow, a simulation-in-a-loop flow based on commercial tools for both the electrical and the mechanical domain has been implemented.

This paper presents a new approach to capacitor placement in differential charge-scaling data converters. Good capacitor matching is crucial for charge-scaling converter resolution. Differential circuits are preferred to single-ended architectures due to improved immunity to noise and variations. The proposed method is based on the analysis of converter static nonlinearity equations. The impact of capacitor variations on converter linearity is minimized by exploiting spatial correlation between devices. Mathematical analysis is completed for two differential analog-to-digital converters. A procedure to obtain a capacitor placement is presented for each circuit. The architectures are compared with respect to linearity and capacitor placement area.

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a novel analytical model for the linearity metrics of a charge scaling digital-to-analog converter. Minimizing the variance of the linearity metrics directs a new chessboard placement method for the capacitor array. Chessboard placement is shown to be superior to the state of the art in consideration of both random and systematic mismatch. The new analytical model is then used to develop a flow for capacitor array sizing.