This paper investigates the uplink massive grant-free random access in low-earth-orbit (LEO) satellite-based Internet-of-Things systems, where accurate joint activity detection and channel estimation (JADCE) is essential for reliable data recovery. However, the resource constraint and high-dynamic characteristic of LEO scenarios pose significant challenges to traditional JADCE schemes in terms of both estimation accuracy and computational complexity. To overcome these limitations, we propose a novel deep-unfolding JADCE framework based on the synergistic multi-stage optimization iterative shrinkage thresholding algorithm network, referred to as SMO-ISTA-Net, to facilitate efficient massive device access. Specifically, we first develop a synergistic attention module, where an inertia-guided optimization strategy is introduced into the gradient descent process to improve convergence stability and adaptability to fast-varying satellite channels. In order to mitigate the temporal feature inconsistency caused by asynchronous access and multi-path propagation, we further design a lightweight cross-attention mechanism that enables efficient channel feature fusion and facilitates multi-stage information interaction. Moreover, we propose a memory-enhanced proximal-mapping module that incorporates a high-throughput short-term memory mechanism into the unfolded structure, so as to significantly reduce information loss and maximize memory retention of the network. Extensive simulations under diverse LEO scenarios demonstrated that our scheme can achieve superior convergence speed, estimation accuracy, and preamble efficiency, while maintaining low computational complexity and short runtime, compared to the state-of-the-art model-driven JADCE schemes.

GPUs have become common in HPC systems to accelerate scientific computing and machine learning applications. Efficiently mapping these applications to rapid evolutions of GPU architectures for high performance is a well-known challenge. Various performance inefficiencies exist in GPU kernels that impede applications from obtaining bare-metal performance. While existing tools are able to measure these inefficiencies, they mostly focus on data collection and presentation, requiring significant manual efforts to understand the root causes for actionable optimization. Thus, we develop DrGPU, a novel profiler that performs top-down analysis to guide GPU code optimization. As its salient feature, DrGPU leverages hardware performance counters available in commodity GPUs to quantify stall cycles, decompose them into various stall reasons, pinpoint root causes, and provide intuitive optimization guidance. With the help of DrGPU, we are able to analyze important GPU benchmarks and applications and obtain nontrivial speedups --- up to 1.77X on V100 and 2.03X on GTX 1650.

Dynamic timing slack has emerged as a compelling opportunity for eliminating inefficiency in ultra-low power embedded systems. This slack arises when all the signals have propagated through logic paths well in advance of the clock signal. When it is properly identified, the system can exploit this unused cycle time for energy savings. In this paper, we describe compiler and architecture co-design that opens new opportunities for timing slack that are otherwise impossible. Through cross-layer optimization, we introduce novel mechanisms in the hardware and in the compiler that work together to improve the benefit of circuit-level timing speculation by effectively squeezing time during execution. This approach is particularly well-suited to tiny embedded devices. Our evaluation on a gate-level model of a complete processor shows that our co-design saves (on average) 40.5% of the original energy consumption (additional 16.5% compared to the existing clock scheduling technique) across 13 workloads while retaining transparency to developers.

Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.

This paper explores a novel associative low power operation where instructions govern the operation of on-chip regulators in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme is developed with energy models formulated for deriving the energy efficiency of the associative operation. The proposed system scheme is demonstrated using a low power microprocessor design with an integrated switched capacitor regulator in 45nm CMOS technology. Simulations on benchmark programs show a power saving of around 14% from the proposed scheme. A novel compiler optimization strategy is also proposed to further improve the energy efficiency.