Process variation (PV) is a conspicuous predicament for submicrometer VLSI circuits. In this paper, we illustrate “choke points” as a vital consequence of PV in the near-threshold computing domain. Choke points are PV affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors induced thereby, we propose dynamic choke sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in the future. We propose two variants of our scheme. Our techniques provide ~55% improvement in performance and ~73% improvement in energy efficiency as compared with popular timing error mitigation scheme, Razor, with minimal area and power overheads.

Process variation is a conspicuous predicament for sub-micron VLSI circuits. In this paper, we illustrate “choke points” as a vital consequence of process variation in the Near Threshold Computing (NTC) domain. Choke points are process variation affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors induced thereby, we propose Dynamic Choke Sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in future. Our scheme provides 25%-160% improvement in performance and 50%-90% improvement in energy efficiency as compared to contemporary timing error mitigation schemes, with minimal area and power overheads.

The emergence of GPGPU applications, bolstered by flexible GPU programming platforms, has created a tremendous challenge in maintaining high energy efficiency in modern GPUs. In this article, we demonstrate that customizing a Streaming Multiprocessor (SM) of a GPU at a lower frequency is significantly more energy efficient compared to employing DVFS on an SM designed for a high-frequency operation. Using a system-level CAD technique, we proposeSSAGA—Streaming Multiprocessors Synthesized for Asymmetric GPGPU Applications—an energy-efficient GPU design paradigm. SSAGA creates architecturally identical SM cores, customized for different voltage-frequency domains. Our rigorous cross-layer methodology demonstrates an average of 20% improvement in energy efficiency over a spatially multitasking GPU across a range of GPGPU applications.

In this paper, we investigate the challenges of preserving energy-efficiency in a Near-Threshold Computing (NTC) GPU. Two key factors can significantly undermine the efficacy of GPUs at NTC: (a) elongated delays at NTC make the GPU applications severely sensitive toMulti-cycle Latency Datapaths (MLDs) within the GPU pipeline; and (b) process variation (PV) at NTC induces a substantial performance variance. To address these emerging challenges, we propose SwiftGPU---an energyefficient GPU design paradigm at NTC. SwiftGPU dynamically adjusts the degree of parallelization, and the speed of the MLDs within each stream core of the GPU. The proposed scheme achieves an average of~15% improvement in energy-efficiency over an ideal PV-free GPU, operating at the Super-Threshold regime. SwiftGPU incurs marginal area, wire-length and power overheads of 0.65%, 2.6% and 3.7%, respectively.