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Forrest Salter

dblp:180/6395 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1964
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 93% Processor architecture and microarchitecture · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › memory circuit design
memory elements		 0.011964
A Ternary Memory Element Using a Tunnel Diode · IEEE Trans. Electron. Comput. 1964
Integrated circuit design
digital circuit design		 0.011960
High-Speed Transistorized Adder for a Digital Computer · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design › arithmetic circuit design › adder design
high-speed adder		 0.011960
High-Speed Transistorized Adder for a Digital Computer · IRE Trans. Electron. Comput. 1960
Integrated circuit design › analog and mixed-signal circuits
tunnel diode circuit		 0.011964
A Ternary Memory Element Using a Tunnel Diode · IEEE Trans. Electron. Comput. 1964
Processor architecture and microarchitecture
arithmetic unit		 0.011960
High-Speed Transistorized Adder for a Digital Computer · IRE Trans. Electron. Comput. 1960

Methods — techniques the papers use, named apart from their topics

tunnel diode · 0.0transistor logic design · 0.0RCTL circuitry · 0.0
YearPublicationVenuePosition
1964 A Ternary Memory Element Using a Tunnel Diode
Forrest Salter
 IEEE Trans. Electron. Comput.1
1960 High-Speed Transistorized Adder for a Digital Computer
abstract
An adder is described that has been developed for the Floating Indexed Point Arithmetic Unit, FLIP, to be used in conjunction with GEORGE, the existing computer built at Argonne National Laboratory. The logic of the high-speed adder and the special circuits required are presented. The adder is parallel and its high speed is made possible by reducing the carry propagation time. Each bit of the adder contributes one transistor to make up a tall AND gate which reduces the carry propagation time to 0.2 μsec. Using this high-speed carry propagation and rather common RCTL transistor circuitry, it is possible to complete an addition in less than 0.25 μsec.
Forrest Salter
 IRE Trans. Electron. Comput.1