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Stuart B. Lerner

dblp:180/6524 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1965
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits		 0.011965
Hazard Correction in Asynchronous Sequential Circuits · IEEE Trans. Electron. Comput. 1965
Integrated circuit design › digital circuit design
hazard correction		 0.011965
Hazard Correction in Asynchronous Sequential Circuits · IEEE Trans. Electron. Comput. 1965
YearPublicationVenuePosition
1965 Hazard Correction in Asynchronous Sequential Circuits
Stuart B. Lerner
 IEEE Trans. Electron. Comput.1