The Long-Range (LoRa) system for the Internet of Things (IoT) has proved effective in infrastructure, energy consumption, resource reduction, and pollution control. However, in terms of security, LoRa faces several challenges. LoRa has a centralised architecture where all sensor data is transmitted to a fog (edge) server via LoRa gateways and processed at the fog server. This exposes sensitive sensor data to some major security threats, such as data tampering, injection of fake data and data loss. LoRa gateways in such architecture simply forward packets to the server. We present a blockchain-based open-source solution for LoRa Gateways that addresses the security vulnerabilities of this architecture and utilises the computing and storage resources of LoRa Gateways. The main challenges in implementing blockchain at LoRa gateways are limited processing, storage capabilities and battery power. The number of gateway nodes improves security and reduces the workload on the fog server. With the introduction of packet processing at the gateway, unnecessary packets are dropped at the gateway itself. Simulation results depict a reduced CPU usage at the fog server for up to 2 % when 16 end devices are being used. Further, our work reduces the overall packet handling time by up to 17% compared to existing works.

The growth of the Internet of Things (IoT) has led to an increased demand for contactless payment via IoT devices. However, machine-to-machine (M2M) payment in the IoT has been limited by poor centralized transaction management, given the distributed nature of the IoT, which results in massive communication overhead. Blockchain technology provides a promising solution for M2M payments in the IoT, but the current blockchain-based solutions for contactless payment lack security and scalability. To address this, a new customised Committee Member Auction mechanism has been proposed that is both safe and scalable for resource-constrained IoT devices. This mechanism also reduces the block mining time by integrating the BLAKE hashing algorithm, as opposed to SHA-256. The proposed framework was implemented utilizing an ESP32 microcontroller and RC522 RFID reader to record over 100 transactions each for SHA-256 and Blake. The results obtained validate that Blake hashing algorithm along with Bidirectional blockchain outperforms SHA-256 by reducing 30% of mining time. Besides improved mining efficiency, this scheme is also found to be resistant against Long Range Attack, Double Spend Attack and Eclipse attack. The proposed scheme thus offers a more secure and scalable option for contactless payments in IoT systems.

The linearity of data converters fabricated in modern CMOS processes is typically limited by device mismatch. The dispersion in device placement primarily determines the extent of matching and hence, the chip yield. Till date, there exists no straightforward approach to precisely quantify dispersion over an array of identically laid out devices. The current research formulates new measures to quantify dispersion in device placement. The incorporation of such measures in traditional CAD optimization results in similar or even better correlation coefficients, but with a lighter computational footprint. This facilitates for faster optimization of large device placements without the need for high end processors.

This paper presents an ensemble part-of-speech tagging approach for source code identifiers. Ensemble tagging is a technique that uses machine-learning and the output from multiple part-of-speech taggers to annotate natural language text at a higher quality than the part-of-speech taggers are able to obtain independently. Our ensemble uses three state-of-the-art part-of-speech taggers: SWUM, POSSE, and Stanford. We study the quality of the ensemble’s annotations on five different types of identifier names: function, class, attribute, parameter, and declaration statement at the level of both individual words and full identifier names. We also study and discuss the weaknesses of our tagger to promote the future amelioration of these problems through further research. Our results show that the ensemble achieves 75 percent accuracy at the identifier level and 84-86 percent accuracy at the word level. This is an increase of +17% points at the identifier level from the closest independent part-of-speech tagger.

High speed data converter architectures such as pipelined analog-to-digital-converters (ADCs) typically consist of large capacitor arrays that are highly susceptible to systematic errors. Although significant efforts have been made in the literature to compensate linear and parabolic errors, the rotated parabolic components are less explored. These rotated parabolic components are responsible for spurious harmonics at the output of the converter, thereby degrading the linearity. In this article, we have investigated the origin of these rotated components, their impact on conversion linearity and discussed strategies to mitigate them. A placement technique along with one track routing solution, is proposed for complete compensation of the systematic errors. An algorithm is also provided to extend this technique to higher resolutions. The proposed technique is verified on the model of pipelined ADC, as well as current steering DAC. The incorporation of such technique results in near ideal linearity performance.