This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

On-chip testing for analog/mixed signal circuits helps improve reliability of safety-critical systems by enabling infield testing. It also alleviates the problems of increasing test costs. A low-cost high accuracy stimulus generator for on-chip spectral testing is proposed. The generator uses a low-cost DAC which requires minimal design and re-engineering efforts, in conjunction with INL based digital pre-distortion to calibrate its linearity performance. DAC output measurement, DAC INL estimation and DAC linearity calibration are all performed on-chip. Measurement results in 40nm bulk CMOS technology demonstrate that the circuit is capable of producing a rail-to-rail differential signal with THD of -75 dB and SFDR of 79dB. The proposed solution is a major step forward in demonstrating the feasibility of synthesizable built-in-test solutions for high-accuracy embedded analog and mixed signal functions.

Multisite (parallel) testing is becoming more widely used in analog and mixed-signal testing to increase throughput and meet high customer demand. However, site-to-site variations are inevitable due to the complexities involved in massive multisite test board design. Sites with pronounced systematic errors (issue sites) lead to measurements not reflecting the true performance of the device under test (DUT), causing potential yield loss and test escapes. Traditional mechanical repair of such sites is expensive, time-consuming, and labor-intensive. Polynomial transformation methods have been successfully explored to calibrate measurements at issue test sites. However, its rigid application could lead to overfitting or underfitting without foreknowledge of the nature and level of induced errors. This paper presents an optimal order polynomial transformation method that is flexible and self-adaptive. It uses a predefined error metric to find the optimal-order of the transformation polynomial and provides optimal calibration coefficients. Simulations and real test data are used to evaluate the effectiveness of the proposed method. Further validation is also provided by comparing the die measurements of issue sites after calibration against a more accurate reference.

The multisite test hardware is built with imperfect elements. Hence, like all measuring instruments, measurement errors are induced by test sites. These errors (random and systematic) are usually insignificant to guarantee test quality. However, as the number of test sites on the multisite tester increases (to further increase throughput), the induced systematic errors for some test sites become pronounced. The measurements of some test sites no longer reflect the true performance of the device under test (DUT), and the likelihood of yield loss or potential test escapes is increased. While multisite test hardware troubleshooting and correction can be difficult, time-consuming, and expensive, it is much easier to calibrate the measurements of issue sites (test sites with unacceptable systematic variations). This paper proposes a least-squares method for systematic hardware error identification and calibration. This method uses linear regression to compare the distribution of measurements at each test site to that of a reference (true and expected) distribution as a means to identify systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware systematic variations and further guarantee test quality. MATLAB® experiments indicate our approach outperforms existing methods in terms of accuracy. Application of the method to real test data confirms the effectiveness and robustness of the method without compromising test quality.

Multisite testing has become a proven method to reduce test time and costs for integrated circuits (IC). However, the technique suffers from site-to-site variations, especially when a large number of test sites are involved. It becomes imperative to identify issue sites that exhibit unacceptable variations to prevent yield loss or incorrect passing of faulty devices. By correctly identifying the true probability distribution of tested specifications, identification of issue sites becomes easier. We introduce an ordinal optimization-based algorithm to select the right sites to estimate the true distribution in situations where it is difficult or impossible to find the true distribution for tested specifications. Using both simulation and real-world ATE test data, we demonstrate that this approach yields good results.

Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize in this paper that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.

Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.

Timing jitter is a crucial factor for high speed and high performance ADCs. Random clock jitter and the intrinsic aperture jitter of the ADC raise the noise floor and make it difficult to accurately estimate ADC specifications from the output spectrum. The stringent requirement of coherent sampling imposes further constraints on the test equipment. The proposed method significantly relaxes clock jitter and coherent sampling requirements by utilizing a dual channel test setup. The algorithm can efficiently separate and estimate noise, intrinsic ADC aperture jitter and random clock jitter, while allowing for arbitrary non-coherency in sampling. Simulation results of ADCs of different resolutions and sub-picosecond jitter levels validate the functionality and accuracy of the method.

This paper presents a Concurrent Sampling (CS) method for measuring a multitude of analog DC voltages concurrently using local digitization. Boolean results after digitization are routed in an IJTAG compatible fashion. Analog quantities are no longer routed across the die, thus overcoming several limitations of Analog Test Buses. Furthermore, the proposed method enables real-time measurement of analog voltages, thus addressing a growing need for Automotive test and reliability. The proposed method is applied to an analog circuit consisting of widely used analog blocks such as a bandgap reference and an operational amplifier. Transistor level simulation results demonstrate that the proposed method is functional and the drawbacks of the ATB are no longer present.

Production test of parametric specifications is a significant contributor to the overall cost of build for analog and mixed-signal products. Data converters (ADCs and DACs) in particular are critical components of integrated circuits used in control/actuation and sensing applications. If left un-optimized, their production test time often dominates the overall system-on-chip (SoC) test time. In this paper, we specifically focus on static linearity test of DACs and propose architecture-aware test methods that are combined with best-in-class fast linearity test concepts in the literature to minimize test time without compromising test quality. The proposed methods exploit the hypothesis that the number of device errors which contribute to linearity errors can be captured by a significantly fewer number of variables than the number of codes at which linearity needs to be tested. We introduce a new time and memory efficient method called Extrapolated Reconstruction (ER) to calculate DAC INL and DNL, based on the segmented model introduced in uSMILE. We also demonstrate that since the segmented model techniques do not account for interpolation, they are not suitable for interpolated DACs. We thus develop an interpolated segmented model and enhance both uSMILE and ER to obtain two new methods that provide correct estimations for interpolated DACs. A linearity test time reduction of 15×-20× was seen in actual silicon measurement results for multiple 12-bit DACs and >100× was seen in simulation case studies for many 16-bit DACs.

This paper presents a clock-less digital pulse stretcher which takes a short pulse as input and produces a detectable pulse that is longer than a required minimum duration. The proposed structure has high sensitivity to input pulse width and height and is capable of detecting deep sub-nanosecond pulses. This enables a wide variety of applications ranging from characterization of radiation-induced single-event transients to detection of glitch attacks and tamper resistance for security. Implementation of the proposed pulse stretcher in a 130nm process validates the analytical relationships between the input and output pulse. Simulation results show that the design can capture an input pulse with width larger than 50ps and height greater than 300mV. The shortest pulse that can be detected by the design can readily scale down with technology due to the digital nature of the circuitry.

A method for separating and accurately estimating ADC noise, aperture jitter, and clock jitter is presented for ADC testing and characterization. This significantly relaxes clock jitter requirements and removes the need for high precision test instruments, but still allows ADC specifications like SNR, SNDR and ENOB to be accurately estimated.

A systematic method is proposed to approach complete fault coverage for catastrophic faults in analog circuits. In the proposed method, a fault propagation graph is first created from the circuit netlist. Standard graph theory techniques are then employed to identify a minimal set of observation points (MOP) such that, by monitoring these points, complete fault coverage can be achieved, i.e., all potential catastrophic faults of the circuit can be detected theoretically. The developed method is valuable because of the increasingly critical quality requirements for modern IC applications and the lack of existing methods that can achieve sub-ppm test escapes in the state-of-the-art. A widely used benchmark circuit, a CMOS operational amplifier, is utilized to demonstrate and validate the method. Simulation results show that all catastrophic faults can be detected by monitoring the identified MOP.

Accurately characterizing linearity performance of high resolution Analog-to-Digital Converters (ADCs) has been a challenging task for many years, as providing input signals whose purity is beyond ADC under test becomes harder and harder as the ADC performance becomes better. This paper proposes a novel method that uses impure test signals to accurately test linearity performance of ADC. Two nonlinear sinusoidal signals with a constant offset in between are applied to the ADC under test to obtain two output data. By identifying nonlinearities from the input and removing these stimulus errors, accurate linearity performance can be obtained. Compared with previous SEIR methods, which is vulnerable to flicker noise inherited in the input signals, the new method uses impure sinusoidal signals instead of ramp signals. Using only -40 to -70dB purity sinusoidal signals, without any Center Symmetric Interleaving (CSI) or Interleaving pattern, the proposed method is much easier to implement, and it can tolerate the influence of flicker noise, while achieving ± 0.8 least significant bit (LSB) estimation error, which is in the similar level when a pure sinusoidal is used for the same ADC linearity test. The proposed method is analyzed in detail and comparisons are made between previous SEIR methods. The effectiveness and robustness of the proposed method against flicker noise is verified through various simulations. The proposed method helps reduce the production test cost, and simplify the test setup for high resolution ADC linearity test, which is suitable for cost-effective on-chip implementation.