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Kao-Chi Lee

dblp:180/6701 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design for manufacturability
0.312018
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Electronic design automation › hardware test
integrated circuit testing
0.312018
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018

Methods — techniques the papers use, named apart from their topics

model-based random forest · 0.3SPICE simulation · 0.3
YearPublicationVenuePosition
2018 A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement
abstract
To measure the variation of device Vtrequires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased only on the combined Idmeasured from parallel connected DUTs. The proposed framework can further minimize the total number of Idmeasurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting either Vtmean or Vtvariance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3 × speedup on overall test time for test structures with 800 DUTs.
Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango Chia-Tso Chao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2017 Fast WAT test structure for measuring Vt variance based on latch-based comparators
abstract
As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-under-test (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-amplifier-based test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.
Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao
VTS1
2016 Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
abstract
To measure the variation of device Vtrequires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased on only the combined Idmeasured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vtmean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Idmeasurement per DUT.
Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango Chia-Tso Chao
VTS2