Demo Data from VLDB 2026 / reviewers in the wild / expert
Sung-Chu Yu
dblp:180/6746
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design for manufacturability |
0.3 | 1 | 2018 | A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › hardware test
integrated circuit testing |
0.3 | 1 | 2018 | A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
model-based random forest · 0.3SPICE simulation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id MeasurementabstractTo measure the variation of device Vtrequires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased only on the combined Idmeasured from parallel connected DUTs. The proposed framework can further minimize the total number of Idmeasurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting either Vtmean or Vtvariance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a 120.3 × speedup on overall test time for test structures with 800 DUTs. Chien-Hsueh Lin, Chih-Ying Tsai, Kao-Chi Lee, Sung-Chu Yu, Wen-Rong Liau, Alex Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango Chia-Tso Chao |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2016 | Predicting Vt mean and variance from parallel Id measurement with model-fitting techniqueabstractTo measure the variation of device Vtrequires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vtfor a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vtbased on only the combined Idmeasured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vtmean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Idmeasurement per DUT. Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango Chia-Tso Chao |
VTS | 4 |